Matt Arsenault cc46d00a86

AMDGPU: Form v2f16 minimum3/maximum3 on gfx950 (#128123)

2025-02-21 12:11:51 +07:00

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AArch64

[GlobalISel][AArch64] Fix fptoi.sat lowering. (#127901)

2025-02-20 12:22:11 +00:00

AMDGPU

AMDGPU: Form v2f16 minimum3/maximum3 on gfx950 (#128123)

2025-02-21 12:11:51 +07:00

ARC

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ARM

[IR] Remove mul constant expression (#127046)

2025-02-14 09:28:57 +01:00

AVR

PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)

2025-02-05 23:29:02 +07:00

BPF

PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)

2025-02-05 23:29:02 +07:00

CSKY

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DirectX

[HLSL] Add more tests to root signature metadata extraction (#127283)

2025-02-18 11:40:29 -08:00

Generic

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Hexagon

[Hexagon] Explicitly truncate constant in UAddSubO (#127360)

2025-02-17 09:30:48 -06:00

Inputs

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Lanai

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LoongArch

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

M68k

[M68k] always use movem for register spills (#106715)

2025-01-31 19:42:40 -06:00

Mips

[Mips] Reserve hardware register HWR2 (#127775)

2025-02-20 20:53:30 +08:00

MIR

[NVPTX] Remove redundant addressing mode instrs (#128044)

2025-02-20 14:51:06 -08:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Remove redundant addressing mode instrs (#128044)

2025-02-20 14:51:06 -08:00

PowerPC

[SDAG] Add missing ppc_fp128 ExpandFloatRes legalization for modf (#127895)

2025-02-20 09:50:16 +07:00

RISCV

[RISCV] Recognize VLA shift pairs from shuffle masks (#127710)

2025-02-20 07:50:49 -08:00

SPARC

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

SPIRV

[SPIR-V] Initial implementation of SPV_INTEL_long_composites (#126545)

2025-02-20 16:09:06 +01:00

SystemZ

[SystemZ] Add codegen support for llvm.roundeven

2025-02-14 00:10:37 +01:00

Thumb

[TargetLowering] Improve one signature of forceExpandWideMUL. (#123991)

2025-01-23 12:49:35 -08:00

Thumb2

[ARM] Fix calling convention for __fp16 with big-endian (#126741)

2025-02-13 09:09:29 +00:00

VE

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

WebAssembly

[WebAssembly] Enable interleaved memory accesses (#125696)

2025-02-17 09:09:52 +00:00

WinCFGuard

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WinEH

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X86

[X86] combineX86ShufflesRecursively - peek through one use bitcasts to find additional (free) extract_subvector nodes

2025-02-20 13:49:49 +00:00

XCore

[llvm] Remove br i1 undef in some llvm/test/CodeGen tests (#126811)

2025-02-12 09:19:00 +00:00

Xtensa

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