Janek van Oirschot cc98b35d0d

[AMDGPU] Masked load vectortype test (#129703)

2025-03-06 17:02:07 +00:00

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AArch64

[NFC][LLVM] Refactor llvm/test/CodeGen/AArch64/sve{2}-fcopysign.ll

2025-03-06 12:53:40 +00:00

AMDGPU

[AMDGPU] Masked load vectortype test (#129703)

2025-03-06 17:02:07 +00:00

ARC

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ARM

SplitKit: Take register class directly from instruction definition (#129727)

2025-03-06 20:06:35 +07:00

AVR

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BPF

[BPF] Add load-acquire and store-release instructions under -mcpu=v4 (#108636)

2025-03-04 09:19:39 -08:00

CSKY

[CSKY] Update fp16-promote.ll test (NFC)

2025-03-05 12:42:32 +01:00

DirectX

[HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (#127137)

2025-03-05 17:04:10 -08:00

Generic

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Hexagon

[CodeGen][NewPM] Port MachineSink to NPM (#115434)

2025-03-03 15:49:37 +05:30

Inputs

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Lanai

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LoongArch

[LoongArch] Relax the restrictions of inlineasm operand modifier 'u' and 'w' (#129864)

2025-03-06 16:17:12 +08:00

M68k

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Mips

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MIR

[win] Enable test/CodeGen/MIR/AArch64 on Windows (#122832)

2025-03-03 09:54:28 -08:00

MLRegAlloc

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MSP430

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NVPTX

[NVPTX] Add Intrinsics for discard.* (#128404)

2025-03-03 22:53:49 +05:30

PowerPC

[PowerPC] hoist xxspltib out of loop body (#127121)

2025-03-03 11:14:02 -05:00

RISCV

[RISCV] Add Qualcomm uC Xqcibm (Bit Manipulation) extension (#129504)

2025-03-06 12:01:53 +05:30

SPARC

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SPIRV

[HLSL] [DXIL] Implement the AddUint64 HLSL function and the UAddc DXIL op (#127137)

2025-03-05 17:04:10 -08:00

SystemZ

[CodeGen][NPM] Port ExpandPostRAPseudos to NPM (#129509)

2025-03-04 11:49:09 +05:30

Thumb

[RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (#120557)

2025-03-03 11:06:15 +05:30

Thumb2

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VE

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WebAssembly

[WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (#128564)

2025-02-26 14:05:00 -08:00

WinCFGuard

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WinEH

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X86

InferAddressSpaces: Replace undef with poison in tests (#130083)

2025-03-06 23:20:46 +07:00

XCore

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Xtensa

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