cd269fee05
This both reapplies #118734, the initial attempt at this, and updates it significantly. First, it uses the newly added `StringTable` abstraction for string tables, and simplifies the construction to build the string table and info arrays separately. This should reduce any `constexpr` compile time memory or CPU cost of the original PR while significantly improving the APIs throughout. It also restructures the builtins to support sharding across several independent tables. This accomplishes two improvements from the original PR: 1) It improves the APIs used significantly. 2) When builtins are defined from different sources (like SVE vs MVE in AArch64), this allows each of them to build their own string table independently rather than having to merge the string tables and info structures. 3) It allows each shard to factor out a common prefix, often cutting the size of the strings needed for the builtins by a factor two. The second point is important both to allow different mechanisms of construction (for example a `.def` file and a tablegen'ed `.inc` file, or different tablegen'ed `.inc files), it also simply reduces the sizes of these tables which is valuable given how large they are in some cases. The third builds on that size reduction. Initially, we use this new sharding rather than merging tables in AArch64, LoongArch, RISCV, and X86. Mostly this helps ensure the system works, as without further changes these still push scaling limits. Subsequent commits will more deeply leverage the new structure, including using the prefix capabilities which cannot be easily factored out here and requires deep changes to the targets.
187 lines
6.0 KiB
C++
187 lines
6.0 KiB
C++
//===--- SystemZ.cpp - Implement SystemZ target feature support -----------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements SystemZ TargetInfo objects.
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//
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//===----------------------------------------------------------------------===//
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#include "SystemZ.h"
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#include "clang/Basic/Builtins.h"
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#include "clang/Basic/LangOptions.h"
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#include "clang/Basic/MacroBuilder.h"
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#include "clang/Basic/TargetBuiltins.h"
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#include "llvm/ADT/StringSwitch.h"
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using namespace clang;
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using namespace clang::targets;
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static constexpr int NumBuiltins =
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clang::SystemZ::LastTSBuiltin - Builtin::FirstTSBuiltin;
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static constexpr llvm::StringTable BuiltinStrings =
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CLANG_BUILTIN_STR_TABLE_START
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#define BUILTIN CLANG_BUILTIN_STR_TABLE
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#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_STR_TABLE
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#include "clang/Basic/BuiltinsSystemZ.def"
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;
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static constexpr auto BuiltinInfos = Builtin::MakeInfos<NumBuiltins>({
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#define BUILTIN CLANG_BUILTIN_ENTRY
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#define TARGET_BUILTIN CLANG_TARGET_BUILTIN_ENTRY
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#include "clang/Basic/BuiltinsSystemZ.def"
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});
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const char *const SystemZTargetInfo::GCCRegNames[] = {
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"r0", "r1", "r2", "r3", "r4", "r5", "r6", "r7",
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"r8", "r9", "r10", "r11", "r12", "r13", "r14", "r15",
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"f0", "f2", "f4", "f6", "f1", "f3", "f5", "f7",
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"f8", "f10", "f12", "f14", "f9", "f11", "f13", "f15",
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/*ap*/"", "cc", /*fp*/"", /*rp*/"", "a0", "a1",
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"v16", "v18", "v20", "v22", "v17", "v19", "v21", "v23",
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"v24", "v26", "v28", "v30", "v25", "v27", "v29", "v31"
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};
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const TargetInfo::AddlRegName GCCAddlRegNames[] = {
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{{"v0"}, 16}, {{"v2"}, 17}, {{"v4"}, 18}, {{"v6"}, 19},
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{{"v1"}, 20}, {{"v3"}, 21}, {{"v5"}, 22}, {{"v7"}, 23},
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{{"v8"}, 24}, {{"v10"}, 25}, {{"v12"}, 26}, {{"v14"}, 27},
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{{"v9"}, 28}, {{"v11"}, 29}, {{"v13"}, 30}, {{"v15"}, 31}
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};
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ArrayRef<const char *> SystemZTargetInfo::getGCCRegNames() const {
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return llvm::ArrayRef(GCCRegNames);
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}
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ArrayRef<TargetInfo::AddlRegName> SystemZTargetInfo::getGCCAddlRegNames() const {
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return llvm::ArrayRef(GCCAddlRegNames);
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}
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bool SystemZTargetInfo::validateAsmConstraint(
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const char *&Name, TargetInfo::ConstraintInfo &Info) const {
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switch (*Name) {
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default:
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return false;
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case 'Z':
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switch (Name[1]) {
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default:
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return false;
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case 'Q': // Address with base and unsigned 12-bit displacement
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case 'R': // Likewise, plus an index
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case 'S': // Address with base and signed 20-bit displacement
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case 'T': // Likewise, plus an index
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break;
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}
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[[fallthrough]];
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case 'a': // Address register
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case 'd': // Data register (equivalent to 'r')
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case 'f': // Floating-point register
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case 'v': // Vector register
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Info.setAllowsRegister();
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return true;
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case 'I': // Unsigned 8-bit constant
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case 'J': // Unsigned 12-bit constant
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case 'K': // Signed 16-bit constant
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case 'L': // Signed 20-bit displacement (on all targets we support)
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case 'M': // 0x7fffffff
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return true;
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case 'Q': // Memory with base and unsigned 12-bit displacement
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case 'R': // Likewise, plus an index
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case 'S': // Memory with base and signed 20-bit displacement
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case 'T': // Likewise, plus an index
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Info.setAllowsMemory();
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return true;
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}
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}
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struct ISANameRevision {
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llvm::StringLiteral Name;
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int ISARevisionID;
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};
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static constexpr ISANameRevision ISARevisions[] = {
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{{"arch8"}, 8}, {{"z10"}, 8},
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{{"arch9"}, 9}, {{"z196"}, 9},
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{{"arch10"}, 10}, {{"zEC12"}, 10},
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{{"arch11"}, 11}, {{"z13"}, 11},
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{{"arch12"}, 12}, {{"z14"}, 12},
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{{"arch13"}, 13}, {{"z15"}, 13},
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{{"arch14"}, 14}, {{"z16"}, 14},
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{{"arch15"}, 15},
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};
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int SystemZTargetInfo::getISARevision(StringRef Name) const {
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const auto Rev =
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llvm::find_if(ISARevisions, [Name](const ISANameRevision &CR) {
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return CR.Name == Name;
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});
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if (Rev == std::end(ISARevisions))
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return -1;
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return Rev->ISARevisionID;
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}
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void SystemZTargetInfo::fillValidCPUList(
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SmallVectorImpl<StringRef> &Values) const {
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for (const ISANameRevision &Rev : ISARevisions)
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Values.push_back(Rev.Name);
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}
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bool SystemZTargetInfo::hasFeature(StringRef Feature) const {
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return llvm::StringSwitch<bool>(Feature)
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.Case("systemz", true)
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.Case("arch8", ISARevision >= 8)
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.Case("arch9", ISARevision >= 9)
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.Case("arch10", ISARevision >= 10)
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.Case("arch11", ISARevision >= 11)
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.Case("arch12", ISARevision >= 12)
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.Case("arch13", ISARevision >= 13)
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.Case("arch14", ISARevision >= 14)
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.Case("arch15", ISARevision >= 15)
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.Case("htm", HasTransactionalExecution)
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.Case("vx", HasVector)
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.Default(false);
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}
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unsigned SystemZTargetInfo::getMinGlobalAlign(uint64_t Size,
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bool HasNonWeakDef) const {
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// Don't enforce the minimum alignment on an external or weak symbol if
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// -munaligned-symbols is passed.
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if (UnalignedSymbols && !HasNonWeakDef)
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return 0;
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return MinGlobalAlign;
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}
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void SystemZTargetInfo::getTargetDefines(const LangOptions &Opts,
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MacroBuilder &Builder) const {
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Builder.defineMacro("__s390__");
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Builder.defineMacro("__s390x__");
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Builder.defineMacro("__zarch__");
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Builder.defineMacro("__LONG_DOUBLE_128__");
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Builder.defineMacro("__ARCH__", Twine(ISARevision));
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_1");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_2");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_4");
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Builder.defineMacro("__GCC_HAVE_SYNC_COMPARE_AND_SWAP_8");
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if (HasTransactionalExecution)
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Builder.defineMacro("__HTM__");
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if (HasVector)
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Builder.defineMacro("__VX__");
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if (Opts.ZVector)
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Builder.defineMacro("__VEC__", "10305");
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}
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llvm::SmallVector<Builtin::InfosShard>
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SystemZTargetInfo::getTargetBuiltins() const {
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return {{&BuiltinStrings, BuiltinInfos}};
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}
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