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llvm-project/llvm/test/CodeGen/AMDGPU/fshl.ll
Anshil Gandhi fbdf8ab590
[LSV] Merge contiguous chains across scalar types (#154069) 
This change enables the LoadStoreVectorizer to merge and vectorize
contiguous chains even when their scalar element types differ, as long
as the total bitwidth matches. To do so, we rebase offsets between
chains, normalize value types to a common integer type, and insert the
necessary casts around loads and stores. This uncovers more
vectorization opportunities and explains the expected codegen updates
across AMDGPU tests.

Key changes:
- Chain merging
  - Build contiguous subchains and then merge adjacent ones when:
- They refer to the same underlying pointer object and address space.
    - They are either all loads or all stores.
    - A constant leader-to-leader delta exists.
- Rebasing one chain into the other's coordinate space does not overlap.
    - All elements have equal total bit width.
- Rebase the second chain by the computed delta and append it to the
first.

- Type normalization and casting
- Normalize merged chains to a common integer type sized to the total
bits.
- For loads: create a new load of the normalized type, copy metadata,
and cast back to the original type for uses if needed.
  - For stores: bitcast the value to the normalized type and store that.
- Insert zext/trunc for integer size changes; use bit-or-pointer casts
when sizes match.

- Cleanups
  - Erase replaced instructions and DCE pointer operands when safe.
- New helpers: computeLeaderDelta, chainsOverlapAfterRebase,
rebaseChain, normalizeChainToType, and allElemsMatchTotalBits.

Impact:
- Increases vectorization opportunities across mixed-typed but
size-compatible access chains.
- Large set of expected AMDGPU codegen diffs due to more/changed
vectorization.

This PR resolves #97715.
2025-12-01 23:05:17 -05:00

958 lines
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LLVM
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc < %s -mtriple=amdgcn -mcpu=tahiti | FileCheck %s --check-prefix=SI
; RUN: llc < %s -mtriple=amdgcn -mcpu=tonga | FileCheck %s --check-prefix=VI
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx900 | FileCheck %s --check-prefix=GFX9
; RUN: llc < %s -mtriple=r600 -mcpu=redwood | FileCheck %s --check-prefix=R600
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1010 | FileCheck %s --check-prefix=GFX10
; RUN: llc < %s -mtriple=amdgcn -mcpu=gfx1100 | FileCheck %s --check-prefix=GFX11
declare i32 @llvm.fshl.i32(i32, i32, i32) nounwind readnone
declare <2 x i32> @llvm.fshl.v2i32(<2 x i32>, <2 x i32>, <2 x i32>) nounwind readnone
declare <4 x i32> @llvm.fshl.v4i32(<4 x i32>, <4 x i32>, <4 x i32>) nounwind readnone
define amdgpu_kernel void @fshl_i32(ptr addrspace(1) %in, i32 %x, i32 %y, i32 %z) {
; SI-LABEL: fshl_i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0xb
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s8, s1
; SI-NEXT: s_mov_b32 s9, s0
; SI-NEXT: s_lshr_b32 s3, s0, 1
; SI-NEXT: s_lshr_b64 s[0:1], s[8:9], 1
; SI-NEXT: s_not_b32 s2, s2
; SI-NEXT: s_mov_b32 s1, s3
; SI-NEXT: s_and_b32 s2, s2, 31
; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshl_i32:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s6, s1
; VI-NEXT: s_mov_b32 s7, s0
; VI-NEXT: s_lshr_b32 s3, s0, 1
; VI-NEXT: s_not_b32 s2, s2
; VI-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
; VI-NEXT: s_mov_b32 s1, s3
; VI-NEXT: s_and_b32 s2, s2, 31
; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; VI-NEXT: v_mov_b32_e32 v0, s4
; VI-NEXT: v_mov_b32_e32 v1, s5
; VI-NEXT: v_mov_b32_e32 v2, s0
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: fshl_i32:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, s1
; GFX9-NEXT: s_mov_b32 s5, s0
; GFX9-NEXT: s_lshr_b32 s3, s0, 1
; GFX9-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
; GFX9-NEXT: s_not_b32 s2, s2
; GFX9-NEXT: s_mov_b32 s1, s3
; GFX9-NEXT: s_and_b32 s2, s2, 31
; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: global_store_dword v0, v1, s[6:7]
; GFX9-NEXT: s_endpgm
;
; R600-LABEL: fshl_i32:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LSHR T0.Z, KC0[2].Z, 1,
; R600-NEXT: BIT_ALIGN_INT T0.W, KC0[2].Z, KC0[2].W, 1,
; R600-NEXT: NOT_INT * T1.W, KC0[3].X,
; R600-NEXT: BIT_ALIGN_INT T0.X, PV.Z, PV.W, PS,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; GFX10-LABEL: fshl_i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x2c
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, s1
; GFX10-NEXT: s_mov_b32 s5, s0
; GFX10-NEXT: s_lshr_b32 s3, s0, 1
; GFX10-NEXT: s_not_b32 s2, s2
; GFX10-NEXT: s_lshr_b64 s[0:1], s[4:5], 1
; GFX10-NEXT: s_mov_b32 s1, s3
; GFX10-NEXT: s_and_b32 s2, s2, 31
; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: global_store_dword v0, v1, s[6:7]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: fshl_i32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x2c
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s6, s1
; GFX11-NEXT: s_mov_b32 s7, s0
; GFX11-NEXT: s_lshr_b32 s3, s0, 1
; GFX11-NEXT: s_not_b32 s2, s2
; GFX11-NEXT: s_lshr_b64 s[0:1], s[6:7], 1
; GFX11-NEXT: s_mov_b32 s1, s3
; GFX11-NEXT: s_and_b32 s2, s2, 31
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s0
; GFX11-NEXT: global_store_b32 v0, v1, s[4:5]
; GFX11-NEXT: s_endpgm
entry:
%0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 %z)
store i32 %0, ptr addrspace(1) %in
ret void
}
define amdgpu_kernel void @fshl_i32_imm(ptr addrspace(1) %in, i32 %x, i32 %y) {
; SI-LABEL: fshl_i32_imm:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: s_mov_b32 s0, s3
; SI-NEXT: s_mov_b32 s1, s2
; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], 25
; SI-NEXT: v_mov_b32_e32 v0, s0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshl_i32_imm:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, s3
; VI-NEXT: s_mov_b32 s5, s2
; VI-NEXT: s_lshr_b64 s[2:3], s[4:5], 25
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: fshl_i32_imm:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, s3
; GFX9-NEXT: s_mov_b32 s5, s2
; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], 25
; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
; R600-LABEL: fshl_i32_imm:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].W, literal.x,
; R600-NEXT: 25(3.503246e-44), 0(0.000000e+00)
;
; GFX10-LABEL: fshl_i32_imm:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, s3
; GFX10-NEXT: s_mov_b32 s5, s2
; GFX10-NEXT: s_lshr_b64 s[2:3], s[4:5], 25
; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: fshl_i32_imm:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s4, s3
; GFX11-NEXT: s_mov_b32 s5, s2
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_lshr_b64 s[2:3], s[4:5], 25
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
entry:
%0 = call i32 @llvm.fshl.i32(i32 %x, i32 %y, i32 7)
store i32 %0, ptr addrspace(1) %in
ret void
}
define amdgpu_kernel void @fshl_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y, <2 x i32> %z) {
; SI-LABEL: fshl_v2i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s11, 0xf000
; SI-NEXT: s_mov_b32 s10, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s8, s0
; SI-NEXT: s_mov_b32 s9, s1
; SI-NEXT: s_mov_b32 s0, s5
; SI-NEXT: s_mov_b32 s1, s3
; SI-NEXT: s_lshr_b32 s12, s3, 1
; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; SI-NEXT: s_not_b32 s3, s7
; SI-NEXT: s_mov_b32 s1, s12
; SI-NEXT: s_and_b32 s3, s3, 31
; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], s3
; SI-NEXT: s_mov_b32 s5, s2
; SI-NEXT: s_lshr_b32 s1, s2, 1
; SI-NEXT: s_lshr_b64 s[2:3], s[4:5], 1
; SI-NEXT: s_mov_b32 s3, s1
; SI-NEXT: s_not_b32 s1, s6
; SI-NEXT: s_and_b32 s1, s1, 31
; SI-NEXT: s_lshr_b64 s[2:3], s[2:3], s1
; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[8:11], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshl_v2i32:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[0:7], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_mov_b32 s0, s5
; VI-NEXT: s_mov_b32 s1, s3
; VI-NEXT: s_lshr_b32 s8, s3, 1
; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; VI-NEXT: s_not_b32 s3, s7
; VI-NEXT: s_mov_b32 s1, s8
; VI-NEXT: s_and_b32 s3, s3, 31
; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], s3
; VI-NEXT: s_mov_b32 s5, s2
; VI-NEXT: s_lshr_b32 s1, s2, 1
; VI-NEXT: s_lshr_b64 s[2:3], s[4:5], 1
; VI-NEXT: s_mov_b32 s3, s1
; VI-NEXT: s_not_b32 s1, s6
; VI-NEXT: s_and_b32 s1, s1, 31
; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s0
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: fshl_v2i32:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s0, s13
; GFX9-NEXT: s_mov_b32 s1, s11
; GFX9-NEXT: s_lshr_b32 s2, s11, 1
; GFX9-NEXT: s_not_b32 s3, s15
; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX9-NEXT: s_mov_b32 s1, s2
; GFX9-NEXT: s_and_b32 s2, s3, 31
; GFX9-NEXT: s_lshr_b64 s[0:1], s[0:1], s2
; GFX9-NEXT: s_mov_b32 s13, s10
; GFX9-NEXT: s_lshr_b32 s1, s10, 1
; GFX9-NEXT: s_lshr_b64 s[2:3], s[12:13], 1
; GFX9-NEXT: s_mov_b32 s3, s1
; GFX9-NEXT: s_not_b32 s1, s14
; GFX9-NEXT: s_and_b32 s1, s1, 31
; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], s1
; GFX9-NEXT: v_mov_b32_e32 v0, s2
; GFX9-NEXT: v_mov_b32_e32 v1, s0
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX9-NEXT: s_endpgm
;
; R600-LABEL: fshl_v2i32:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LSHR T0.Z, KC0[3].X, 1,
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[3].X, KC0[3].Z, 1,
; R600-NEXT: NOT_INT * T1.W, KC0[4].X,
; R600-NEXT: BIT_ALIGN_INT T0.Y, T0.Z, T0.W, PV.W,
; R600-NEXT: LSHR T0.Z, KC0[2].W, 1,
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[2].W, KC0[3].Y, 1,
; R600-NEXT: NOT_INT * T1.W, KC0[3].W,
; R600-NEXT: BIT_ALIGN_INT T0.X, T0.Z, T0.W, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; GFX10-LABEL: fshl_v2i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s0, s13
; GFX10-NEXT: s_mov_b32 s1, s11
; GFX10-NEXT: s_not_b32 s2, s15
; GFX10-NEXT: s_mov_b32 s13, s10
; GFX10-NEXT: s_lshr_b32 s4, s11, 1
; GFX10-NEXT: s_lshr_b32 s5, s10, 1
; GFX10-NEXT: s_not_b32 s6, s14
; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], 1
; GFX10-NEXT: s_and_b32 s7, s2, 31
; GFX10-NEXT: s_lshr_b64 s[2:3], s[12:13], 1
; GFX10-NEXT: s_and_b32 s6, s6, 31
; GFX10-NEXT: s_mov_b32 s3, s5
; GFX10-NEXT: s_mov_b32 s1, s4
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s6
; GFX10-NEXT: s_lshr_b64 s[0:1], s[0:1], s7
; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s0
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[8:9]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: fshl_v2i32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b256 s[0:7], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s8, s5
; GFX11-NEXT: s_mov_b32 s9, s3
; GFX11-NEXT: s_mov_b32 s5, s2
; GFX11-NEXT: s_lshr_b32 s10, s3, 1
; GFX11-NEXT: s_not_b32 s7, s7
; GFX11-NEXT: s_lshr_b32 s11, s2, 1
; GFX11-NEXT: s_not_b32 s6, s6
; GFX11-NEXT: s_lshr_b64 s[2:3], s[8:9], 1
; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
; GFX11-NEXT: s_and_b32 s7, s7, 31
; GFX11-NEXT: s_and_b32 s6, s6, 31
; GFX11-NEXT: s_mov_b32 s5, s11
; GFX11-NEXT: s_mov_b32 s3, s10
; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], s6
; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s7
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: v_mov_b32_e32 v0, s4
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
entry:
%0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> %z)
store <2 x i32> %0, ptr addrspace(1) %in
ret void
}
define amdgpu_kernel void @fshl_v2i32_imm(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {
; SI-LABEL: fshl_v2i32_imm:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[8:9], s[4:5], 0xd
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: s_mov_b32 s0, s9
; SI-NEXT: s_mov_b32 s1, s3
; SI-NEXT: s_mov_b32 s9, s2
; SI-NEXT: s_lshr_b64 s[0:1], s[0:1], 23
; SI-NEXT: s_lshr_b64 s[2:3], s[8:9], 25
; SI-NEXT: v_mov_b32_e32 v0, s2
; SI-NEXT: v_mov_b32_e32 v1, s0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshl_v2i32_imm:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: s_mov_b32 s0, s5
; VI-NEXT: s_mov_b32 s1, s3
; VI-NEXT: s_mov_b32 s5, s2
; VI-NEXT: s_lshr_b64 s[0:1], s[0:1], 23
; VI-NEXT: s_lshr_b64 s[2:3], s[4:5], 25
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s0
; VI-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: fshl_v2i32_imm:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v2, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, s7
; GFX9-NEXT: s_mov_b32 s5, s3
; GFX9-NEXT: s_mov_b32 s7, s2
; GFX9-NEXT: s_lshr_b64 s[2:3], s[4:5], 23
; GFX9-NEXT: s_lshr_b64 s[4:5], s[6:7], 25
; GFX9-NEXT: v_mov_b32_e32 v0, s4
; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX9-NEXT: s_endpgm
;
; R600-LABEL: fshl_v2i32_imm:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].Z, literal.x,
; R600-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[3].Y, literal.x,
; R600-NEXT: 25(3.503246e-44), 0(0.000000e+00)
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; GFX10-LABEL: fshl_v2i32_imm:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, s7
; GFX10-NEXT: s_mov_b32 s7, s2
; GFX10-NEXT: s_mov_b32 s5, s3
; GFX10-NEXT: s_lshr_b64 s[2:3], s[6:7], 25
; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 23
; GFX10-NEXT: v_mov_b32_e32 v0, s2
; GFX10-NEXT: v_mov_b32_e32 v1, s4
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: fshl_v2i32_imm:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b64 s[6:7], s[4:5], 0x34
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s4, s7
; GFX11-NEXT: s_mov_b32 s7, s2
; GFX11-NEXT: s_mov_b32 s5, s3
; GFX11-NEXT: s_lshr_b64 s[2:3], s[6:7], 25
; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 23
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v2, 0 :: v_dual_mov_b32 v1, s4
; GFX11-NEXT: v_mov_b32_e32 v0, s2
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
entry:
%0 = call <2 x i32> @llvm.fshl.v2i32(<2 x i32> %x, <2 x i32> %y, <2 x i32> <i32 7, i32 9>)
store <2 x i32> %0, ptr addrspace(1) %in
ret void
}
define amdgpu_kernel void @fshl_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y, <4 x i32> %z) {
; SI-LABEL: fshl_v4i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_load_dwordx4 s[4:7], s[4:5], 0x15
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s16, s15
; SI-NEXT: s_mov_b32 s17, s11
; SI-NEXT: s_lshr_b32 s18, s11, 1
; SI-NEXT: s_lshr_b64 s[16:17], s[16:17], 1
; SI-NEXT: s_not_b32 s7, s7
; SI-NEXT: s_mov_b32 s17, s18
; SI-NEXT: s_and_b32 s7, s7, 31
; SI-NEXT: s_mov_b32 s15, s10
; SI-NEXT: s_lshr_b64 s[16:17], s[16:17], s7
; SI-NEXT: s_lshr_b32 s7, s10, 1
; SI-NEXT: s_lshr_b64 s[10:11], s[14:15], 1
; SI-NEXT: s_not_b32 s6, s6
; SI-NEXT: s_mov_b32 s11, s7
; SI-NEXT: s_and_b32 s6, s6, 31
; SI-NEXT: s_lshr_b64 s[6:7], s[10:11], s6
; SI-NEXT: s_mov_b32 s10, s13
; SI-NEXT: s_mov_b32 s11, s9
; SI-NEXT: s_lshr_b32 s7, s9, 1
; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 1
; SI-NEXT: s_not_b32 s5, s5
; SI-NEXT: s_mov_b32 s11, s7
; SI-NEXT: s_and_b32 s5, s5, 31
; SI-NEXT: s_mov_b32 s13, s8
; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], s5
; SI-NEXT: s_lshr_b32 s5, s8, 1
; SI-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
; SI-NEXT: s_not_b32 s4, s4
; SI-NEXT: s_mov_b32 s9, s5
; SI-NEXT: s_and_b32 s4, s4, 31
; SI-NEXT: s_lshr_b64 s[4:5], s[8:9], s4
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_mov_b32_e32 v1, s10
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: v_mov_b32_e32 v3, s16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshl_v4i32:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; VI-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s4, s15
; VI-NEXT: s_mov_b32 s5, s11
; VI-NEXT: s_lshr_b32 s16, s11, 1
; VI-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
; VI-NEXT: s_not_b32 s3, s3
; VI-NEXT: s_mov_b32 s5, s16
; VI-NEXT: s_and_b32 s3, s3, 31
; VI-NEXT: s_mov_b32 s15, s10
; VI-NEXT: s_lshr_b64 s[4:5], s[4:5], s3
; VI-NEXT: s_lshr_b32 s3, s10, 1
; VI-NEXT: s_lshr_b64 s[10:11], s[14:15], 1
; VI-NEXT: s_not_b32 s2, s2
; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_and_b32 s2, s2, 31
; VI-NEXT: s_lshr_b64 s[2:3], s[10:11], s2
; VI-NEXT: s_mov_b32 s10, s13
; VI-NEXT: s_mov_b32 s11, s9
; VI-NEXT: s_lshr_b32 s3, s9, 1
; VI-NEXT: s_lshr_b64 s[10:11], s[10:11], 1
; VI-NEXT: s_not_b32 s1, s1
; VI-NEXT: s_mov_b32 s11, s3
; VI-NEXT: s_and_b32 s1, s1, 31
; VI-NEXT: s_mov_b32 s13, s8
; VI-NEXT: s_lshr_b64 s[10:11], s[10:11], s1
; VI-NEXT: s_lshr_b32 s1, s8, 1
; VI-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
; VI-NEXT: s_not_b32 s0, s0
; VI-NEXT: s_mov_b32 s9, s1
; VI-NEXT: s_and_b32 s0, s0, 31
; VI-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
; VI-NEXT: v_mov_b32_e32 v4, s6
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s10
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: v_mov_b32_e32 v3, s4
; VI-NEXT: v_mov_b32_e32 v5, s7
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: fshl_v4i32:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX9-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s4, s15
; GFX9-NEXT: s_mov_b32 s5, s11
; GFX9-NEXT: s_lshr_b32 s16, s11, 1
; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
; GFX9-NEXT: s_not_b32 s3, s3
; GFX9-NEXT: s_mov_b32 s5, s16
; GFX9-NEXT: s_and_b32 s3, s3, 31
; GFX9-NEXT: s_mov_b32 s15, s10
; GFX9-NEXT: s_lshr_b64 s[4:5], s[4:5], s3
; GFX9-NEXT: s_lshr_b32 s3, s10, 1
; GFX9-NEXT: s_lshr_b64 s[10:11], s[14:15], 1
; GFX9-NEXT: s_not_b32 s2, s2
; GFX9-NEXT: s_mov_b32 s11, s3
; GFX9-NEXT: s_and_b32 s2, s2, 31
; GFX9-NEXT: s_lshr_b64 s[2:3], s[10:11], s2
; GFX9-NEXT: s_mov_b32 s10, s13
; GFX9-NEXT: s_mov_b32 s11, s9
; GFX9-NEXT: s_lshr_b32 s3, s9, 1
; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], 1
; GFX9-NEXT: s_not_b32 s1, s1
; GFX9-NEXT: s_mov_b32 s11, s3
; GFX9-NEXT: s_and_b32 s1, s1, 31
; GFX9-NEXT: s_mov_b32 s13, s8
; GFX9-NEXT: s_lshr_b64 s[10:11], s[10:11], s1
; GFX9-NEXT: s_lshr_b32 s1, s8, 1
; GFX9-NEXT: s_lshr_b64 s[8:9], s[12:13], 1
; GFX9-NEXT: s_not_b32 s0, s0
; GFX9-NEXT: s_mov_b32 s9, s1
; GFX9-NEXT: s_and_b32 s0, s0, 31
; GFX9-NEXT: s_lshr_b64 s[0:1], s[8:9], s0
; GFX9-NEXT: v_mov_b32_e32 v0, s0
; GFX9-NEXT: v_mov_b32_e32 v1, s10
; GFX9-NEXT: v_mov_b32_e32 v2, s2
; GFX9-NEXT: v_mov_b32_e32 v3, s4
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX9-NEXT: s_endpgm
;
; R600-LABEL: fshl_v4i32:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 17, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LSHR T0.Z, KC0[4].X, 1,
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, 1,
; R600-NEXT: NOT_INT * T1.W, KC0[6].X,
; R600-NEXT: LSHR T0.Y, KC0[3].W, 1,
; R600-NEXT: BIT_ALIGN_INT T1.Z, KC0[3].W, KC0[4].W, 1,
; R600-NEXT: BIT_ALIGN_INT * T0.W, T0.Z, T0.W, PV.W,
; R600-NEXT: NOT_INT * T1.W, KC0[5].W,
; R600-NEXT: LSHR T1.Y, KC0[3].Z, 1,
; R600-NEXT: BIT_ALIGN_INT T0.Z, T0.Y, T1.Z, PV.W,
; R600-NEXT: BIT_ALIGN_INT * T1.W, KC0[3].Z, KC0[4].Z, 1,
; R600-NEXT: NOT_INT * T2.W, KC0[5].Z,
; R600-NEXT: BIT_ALIGN_INT T0.Y, T1.Y, T1.W, PV.W,
; R600-NEXT: LSHR T1.Z, KC0[3].Y, 1,
; R600-NEXT: BIT_ALIGN_INT * T1.W, KC0[3].Y, KC0[4].Y, 1,
; R600-NEXT: NOT_INT * T2.W, KC0[5].Y,
; R600-NEXT: BIT_ALIGN_INT T0.X, T1.Z, T1.W, PV.W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; GFX10-LABEL: fshl_v4i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x2
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x54
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s4, s15
; GFX10-NEXT: s_mov_b32 s5, s11
; GFX10-NEXT: s_mov_b32 s15, s10
; GFX10-NEXT: s_lshr_b32 s16, s11, 1
; GFX10-NEXT: s_not_b32 s11, s3
; GFX10-NEXT: s_lshr_b32 s17, s10, 1
; GFX10-NEXT: s_not_b32 s10, s2
; GFX10-NEXT: s_lshr_b32 s18, s9, 1
; GFX10-NEXT: s_mov_b32 s2, s13
; GFX10-NEXT: s_mov_b32 s3, s9
; GFX10-NEXT: s_lshr_b32 s19, s8, 1
; GFX10-NEXT: s_mov_b32 s13, s8
; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 1
; GFX10-NEXT: s_lshr_b64 s[8:9], s[14:15], 1
; GFX10-NEXT: s_and_b32 s11, s11, 31
; GFX10-NEXT: s_and_b32 s10, s10, 31
; GFX10-NEXT: s_mov_b32 s5, s16
; GFX10-NEXT: s_mov_b32 s9, s17
; GFX10-NEXT: s_not_b32 s1, s1
; GFX10-NEXT: s_not_b32 s0, s0
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], s11
; GFX10-NEXT: s_lshr_b64 s[8:9], s[8:9], s10
; GFX10-NEXT: s_lshr_b64 s[10:11], s[12:13], 1
; GFX10-NEXT: s_mov_b32 s3, s18
; GFX10-NEXT: s_mov_b32 s11, s19
; GFX10-NEXT: s_and_b32 s0, s0, 31
; GFX10-NEXT: s_and_b32 s5, s1, 31
; GFX10-NEXT: s_lshr_b64 s[0:1], s[10:11], s0
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], s5
; GFX10-NEXT: v_mov_b32_e32 v0, s0
; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: v_mov_b32_e32 v2, s8
; GFX10-NEXT: v_mov_b32_e32 v3, s4
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[6:7]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: fshl_v4i32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_clause 0x2
; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x54
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s6, s15
; GFX11-NEXT: s_mov_b32 s7, s11
; GFX11-NEXT: s_mov_b32 s15, s10
; GFX11-NEXT: s_lshr_b32 s16, s11, 1
; GFX11-NEXT: s_not_b32 s11, s3
; GFX11-NEXT: s_lshr_b32 s17, s10, 1
; GFX11-NEXT: s_not_b32 s10, s2
; GFX11-NEXT: s_lshr_b32 s18, s9, 1
; GFX11-NEXT: s_mov_b32 s2, s13
; GFX11-NEXT: s_mov_b32 s3, s9
; GFX11-NEXT: s_lshr_b32 s19, s8, 1
; GFX11-NEXT: s_mov_b32 s13, s8
; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], 1
; GFX11-NEXT: s_lshr_b64 s[8:9], s[14:15], 1
; GFX11-NEXT: s_and_b32 s11, s11, 31
; GFX11-NEXT: s_and_b32 s10, s10, 31
; GFX11-NEXT: s_mov_b32 s7, s16
; GFX11-NEXT: s_mov_b32 s9, s17
; GFX11-NEXT: s_not_b32 s1, s1
; GFX11-NEXT: s_not_b32 s0, s0
; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 1
; GFX11-NEXT: s_lshr_b64 s[6:7], s[6:7], s11
; GFX11-NEXT: s_lshr_b64 s[8:9], s[8:9], s10
; GFX11-NEXT: s_lshr_b64 s[10:11], s[12:13], 1
; GFX11-NEXT: s_mov_b32 s3, s18
; GFX11-NEXT: s_mov_b32 s11, s19
; GFX11-NEXT: s_and_b32 s0, s0, 31
; GFX11-NEXT: s_and_b32 s7, s1, 31
; GFX11-NEXT: s_lshr_b64 s[0:1], s[10:11], s0
; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], s7
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: v_dual_mov_b32 v0, s0 :: v_dual_mov_b32 v3, s6
; GFX11-NEXT: v_mov_b32_e32 v2, s8
; GFX11-NEXT: global_store_b128 v4, v[0:3], s[4:5]
; GFX11-NEXT: s_endpgm
entry:
%0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> %z)
store <4 x i32> %0, ptr addrspace(1) %in
ret void
}
define amdgpu_kernel void @fshl_v4i32_imm(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {
; SI-LABEL: fshl_v4i32_imm:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s15
; SI-NEXT: s_mov_b32 s5, s11
; SI-NEXT: s_mov_b32 s15, s10
; SI-NEXT: s_mov_b32 s10, s13
; SI-NEXT: s_mov_b32 s11, s9
; SI-NEXT: s_mov_b32 s13, s8
; SI-NEXT: s_lshr_b64 s[4:5], s[4:5], 31
; SI-NEXT: s_lshr_b64 s[6:7], s[14:15], 23
; SI-NEXT: s_lshr_b64 s[10:11], s[10:11], 25
; SI-NEXT: s_lshr_b64 s[8:9], s[12:13], 31
; SI-NEXT: v_mov_b32_e32 v0, s8
; SI-NEXT: v_mov_b32_e32 v1, s10
; SI-NEXT: v_mov_b32_e32 v2, s6
; SI-NEXT: v_mov_b32_e32 v3, s4
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: fshl_v4i32_imm:
; VI: ; %bb.0: ; %entry
; VI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; VI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_mov_b32 s2, s15
; VI-NEXT: s_mov_b32 s3, s11
; VI-NEXT: s_mov_b32 s15, s10
; VI-NEXT: s_mov_b32 s6, s13
; VI-NEXT: s_mov_b32 s7, s9
; VI-NEXT: s_mov_b32 s13, s8
; VI-NEXT: s_lshr_b64 s[2:3], s[2:3], 31
; VI-NEXT: s_lshr_b64 s[4:5], s[14:15], 23
; VI-NEXT: s_lshr_b64 s[6:7], s[6:7], 25
; VI-NEXT: s_lshr_b64 s[8:9], s[12:13], 31
; VI-NEXT: v_mov_b32_e32 v5, s1
; VI-NEXT: v_mov_b32_e32 v0, s8
; VI-NEXT: v_mov_b32_e32 v1, s6
; VI-NEXT: v_mov_b32_e32 v2, s4
; VI-NEXT: v_mov_b32_e32 v3, s2
; VI-NEXT: v_mov_b32_e32 v4, s0
; VI-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: fshl_v4i32_imm:
; GFX9: ; %bb.0: ; %entry
; GFX9-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX9-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v4, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_mov_b32 s2, s15
; GFX9-NEXT: s_mov_b32 s3, s11
; GFX9-NEXT: s_mov_b32 s15, s10
; GFX9-NEXT: s_mov_b32 s6, s13
; GFX9-NEXT: s_mov_b32 s7, s9
; GFX9-NEXT: s_mov_b32 s13, s8
; GFX9-NEXT: s_lshr_b64 s[2:3], s[2:3], 31
; GFX9-NEXT: s_lshr_b64 s[4:5], s[14:15], 23
; GFX9-NEXT: s_lshr_b64 s[6:7], s[6:7], 25
; GFX9-NEXT: s_lshr_b64 s[8:9], s[12:13], 31
; GFX9-NEXT: v_mov_b32_e32 v0, s8
; GFX9-NEXT: v_mov_b32_e32 v1, s6
; GFX9-NEXT: v_mov_b32_e32 v2, s4
; GFX9-NEXT: v_mov_b32_e32 v3, s2
; GFX9-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX9-NEXT: s_endpgm
;
; R600-LABEL: fshl_v4i32_imm:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 9, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[5].X, literal.x,
; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[4].W, literal.x,
; R600-NEXT: 23(3.222986e-44), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[4].Z, literal.x,
; R600-NEXT: 25(3.503246e-44), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[4].Y, literal.x,
; R600-NEXT: 31(4.344025e-44), 0(0.000000e+00)
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; GFX10-LABEL: fshl_v4i32_imm:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_mov_b32 s2, s15
; GFX10-NEXT: s_mov_b32 s3, s11
; GFX10-NEXT: s_mov_b32 s15, s10
; GFX10-NEXT: s_mov_b32 s4, s13
; GFX10-NEXT: s_mov_b32 s5, s9
; GFX10-NEXT: s_mov_b32 s13, s8
; GFX10-NEXT: s_lshr_b64 s[2:3], s[2:3], 31
; GFX10-NEXT: s_lshr_b64 s[6:7], s[14:15], 23
; GFX10-NEXT: s_lshr_b64 s[8:9], s[12:13], 31
; GFX10-NEXT: s_lshr_b64 s[4:5], s[4:5], 25
; GFX10-NEXT: v_mov_b32_e32 v0, s8
; GFX10-NEXT: v_mov_b32_e32 v1, s4
; GFX10-NEXT: v_mov_b32_e32 v2, s6
; GFX10-NEXT: v_mov_b32_e32 v3, s2
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: fshl_v4i32_imm:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_mov_b32 s2, s15
; GFX11-NEXT: s_mov_b32 s3, s11
; GFX11-NEXT: s_mov_b32 s15, s10
; GFX11-NEXT: s_mov_b32 s4, s13
; GFX11-NEXT: s_mov_b32 s5, s9
; GFX11-NEXT: s_mov_b32 s13, s8
; GFX11-NEXT: s_lshr_b64 s[2:3], s[2:3], 31
; GFX11-NEXT: s_lshr_b64 s[6:7], s[14:15], 23
; GFX11-NEXT: s_lshr_b64 s[8:9], s[12:13], 31
; GFX11-NEXT: s_lshr_b64 s[4:5], s[4:5], 25
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v4, 0 :: v_dual_mov_b32 v1, s4
; GFX11-NEXT: v_dual_mov_b32 v0, s8 :: v_dual_mov_b32 v3, s2
; GFX11-NEXT: v_mov_b32_e32 v2, s6
; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-NEXT: s_endpgm
entry:
%0 = call <4 x i32> @llvm.fshl.v4i32(<4 x i32> %x, <4 x i32> %y, <4 x i32> <i32 1, i32 7, i32 9, i32 33>)
store <4 x i32> %0, ptr addrspace(1) %in
ret void
}
; (a ^ b) | a --> a | b
define amdgpu_kernel void @orxor2or1(ptr addrspace(1) %in, i32 %a, i32 %b) {
; SI-LABEL: orxor2or1:
; SI: ; %bb.0:
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b64 s[4:5], s[2:3]
; SI-NEXT: s_lshl_b32 s6, s4, 7
; SI-NEXT: s_or_b32 s6, s5, s6
; SI-NEXT: s_cmp_eq_u32 s6, 0
; SI-NEXT: s_cselect_b32 s4, s4, s5
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: buffer_store_dword v0, off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; VI-LABEL: orxor2or1:
; VI: ; %bb.0:
; VI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; VI-NEXT: s_waitcnt lgkmcnt(0)
; VI-NEXT: s_lshl_b32 s4, s2, 7
; VI-NEXT: s_or_b32 s4, s3, s4
; VI-NEXT: s_cmp_eq_u32 s4, 0
; VI-NEXT: s_cselect_b32 s2, s2, s3
; VI-NEXT: v_mov_b32_e32 v0, s0
; VI-NEXT: v_mov_b32_e32 v1, s1
; VI-NEXT: v_mov_b32_e32 v2, s2
; VI-NEXT: flat_store_dword v[0:1], v2
; VI-NEXT: s_endpgm
;
; GFX9-LABEL: orxor2or1:
; GFX9: ; %bb.0:
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX9-NEXT: v_mov_b32_e32 v0, 0
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
; GFX9-NEXT: s_lshl_b32 s4, s2, 7
; GFX9-NEXT: s_or_b32 s4, s3, s4
; GFX9-NEXT: s_cmp_eq_u32 s4, 0
; GFX9-NEXT: s_cselect_b32 s2, s2, s3
; GFX9-NEXT: v_mov_b32_e32 v1, s2
; GFX9-NEXT: global_store_dword v0, v1, s[0:1]
; GFX9-NEXT: s_endpgm
;
; R600-LABEL: orxor2or1:
; R600: ; %bb.0:
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.X, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LSHL * T0.W, KC0[2].Z, literal.x,
; R600-NEXT: 7(9.809089e-45), 0(0.000000e+00)
; R600-NEXT: OR_INT * T0.W, KC0[2].W, PV.W,
; R600-NEXT: CNDE_INT T0.X, PV.W, KC0[2].Z, KC0[2].W,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; GFX10-LABEL: orxor2or1:
; GFX10: ; %bb.0:
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: s_lshl_b32 s4, s2, 7
; GFX10-NEXT: s_or_b32 s4, s3, s4
; GFX10-NEXT: s_cmp_eq_u32 s4, 0
; GFX10-NEXT: s_cselect_b32 s2, s2, s3
; GFX10-NEXT: v_mov_b32_e32 v1, s2
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: orxor2or1:
; GFX11: ; %bb.0:
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: s_lshl_b32 s4, s2, 7
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(SALU_CYCLE_1)
; GFX11-NEXT: s_or_b32 s4, s3, s4
; GFX11-NEXT: s_cmp_eq_u32 s4, 0
; GFX11-NEXT: s_cselect_b32 s2, s2, s3
; GFX11-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
; GFX11-NEXT: v_dual_mov_b32 v0, 0 :: v_dual_mov_b32 v1, s2
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
%shl = shl i32 %a, 7
%xor = xor i32 %shl, %b
%or = or i32 %a, %xor
%fshl = call i32 @llvm.fshl.i32(i32 %or, i32 %xor, i32 7)
%cond = icmp eq i32 %fshl, 0
%r = select i1 %cond, i32 %a, i32 %b
store i32 %r, ptr addrspace(1) %in
ret void
}
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