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llvm-project/llvm/test/CodeGen/AMDGPU/rotr.ll
Anshil Gandhi fbdf8ab590
[LSV] Merge contiguous chains across scalar types (#154069) 
This change enables the LoadStoreVectorizer to merge and vectorize
contiguous chains even when their scalar element types differ, as long
as the total bitwidth matches. To do so, we rebase offsets between
chains, normalize value types to a common integer type, and insert the
necessary casts around loads and stores. This uncovers more
vectorization opportunities and explains the expected codegen updates
across AMDGPU tests.

Key changes:
- Chain merging
  - Build contiguous subchains and then merge adjacent ones when:
- They refer to the same underlying pointer object and address space.
    - They are either all loads or all stores.
    - A constant leader-to-leader delta exists.
- Rebasing one chain into the other's coordinate space does not overlap.
    - All elements have equal total bit width.
- Rebase the second chain by the computed delta and append it to the
first.

- Type normalization and casting
- Normalize merged chains to a common integer type sized to the total
bits.
- For loads: create a new load of the normalized type, copy metadata,
and cast back to the original type for uses if needed.
  - For stores: bitcast the value to the normalized type and store that.
- Insert zext/trunc for integer size changes; use bit-or-pointer casts
when sizes match.

- Cleanups
  - Erase replaced instructions and DCE pointer operands when safe.
- New helpers: computeLeaderDelta, chainsOverlapAfterRebase,
rebaseChain, normalizeChainToType, and allElemsMatchTotalBits.

Impact:
- Increases vectorization opportunities across mixed-typed but
size-compatible access chains.
- Large set of expected AMDGPU codegen diffs due to more/changed
vectorization.

This PR resolves #97715.
2025-12-01 23:05:17 -05:00

499 lines
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; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py UTC_ARGS: --version 2
; RUN: llc -mtriple=r600 -mcpu=redwood < %s | FileCheck --check-prefixes=R600 %s
; RUN: llc -mtriple=amdgcn < %s | FileCheck -check-prefixes=SI %s
; RUN: llc -mtriple=amdgcn -mcpu=tonga < %s | FileCheck -check-prefixes=GFX8 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1010 < %s | FileCheck -check-prefixes=GFX10 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=+real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-TRUE16 %s
; RUN: llc -mtriple=amdgcn -mcpu=gfx1100 -mattr=-real-true16 < %s | FileCheck -check-prefixes=GFX11,GFX11-FAKE16 %s
define amdgpu_kernel void @rotr_i32(ptr addrspace(1) %in, i32 %x, i32 %y) {
; R600-LABEL: rotr_i32:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 2, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T1.X, T0.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: LSHR * T0.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T1.X, KC0[2].Z, KC0[2].Z, KC0[2].W,
;
; SI-LABEL: rotr_i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s6, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s4, s0
; SI-NEXT: s_mov_b32 s5, s1
; SI-NEXT: v_mov_b32_e32 v0, s3
; SI-NEXT: v_alignbit_b32 v0, s2, s2, v0
; SI-NEXT: buffer_store_dword v0, off, s[4:7], 0
; SI-NEXT: s_endpgm
;
; GFX8-LABEL: rotr_i32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s3
; GFX8-NEXT: v_alignbit_b32 v2, s2, s2, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: flat_store_dword v[0:1], v2
; GFX8-NEXT: s_endpgm
;
; GFX10-LABEL: rotr_i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v0, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v1, s2, s2, s3
; GFX10-NEXT: global_store_dword v0, v1, s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: rotr_i32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: v_mov_b32_e32 v0, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_alignbit_b32 v1, s2, s2, s3
; GFX11-NEXT: global_store_b32 v0, v1, s[0:1]
; GFX11-NEXT: s_endpgm
entry:
%tmp0 = sub i32 32, %y
%tmp1 = shl i32 %x, %tmp0
%tmp2 = lshr i32 %x, %y
%tmp3 = or i32 %tmp1, %tmp2
store i32 %tmp3, ptr addrspace(1) %in
ret void
}
define amdgpu_kernel void @rotr_v2i32(ptr addrspace(1) %in, <2 x i32> %x, <2 x i32> %y) {
; R600-LABEL: rotr_v2i32:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 3, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XY, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].X, KC0[3].X, KC0[3].Z,
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[2].W, KC0[2].W, KC0[3].Y,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; SI-LABEL: rotr_v2i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x9
; SI-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0xd
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: s_mov_b32 s6, s2
; SI-NEXT: s_mov_b32 s7, s3
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: v_mov_b32_e32 v0, s5
; SI-NEXT: v_alignbit_b32 v1, s7, s7, v0
; SI-NEXT: v_mov_b32_e32 v0, s4
; SI-NEXT: v_alignbit_b32 v0, s6, s6, v0
; SI-NEXT: buffer_store_dwordx2 v[0:1], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; GFX8-LABEL: rotr_v2i32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX8-NEXT: s_load_dwordx2 s[4:5], s[4:5], 0x34
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s0
; GFX8-NEXT: v_mov_b32_e32 v2, s5
; GFX8-NEXT: v_mov_b32_e32 v4, s4
; GFX8-NEXT: v_mov_b32_e32 v1, s1
; GFX8-NEXT: v_alignbit_b32 v3, s3, s3, v2
; GFX8-NEXT: v_alignbit_b32 v2, s2, s2, v4
; GFX8-NEXT: flat_store_dwordx2 v[0:1], v[2:3]
; GFX8-NEXT: s_endpgm
;
; GFX10-LABEL: rotr_v2i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[4:5], 0x24
; GFX10-NEXT: s_load_dwordx2 s[6:7], s[4:5], 0x34
; GFX10-NEXT: v_mov_b32_e32 v2, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v1, s3, s3, s7
; GFX10-NEXT: v_alignbit_b32 v0, s2, s2, s6
; GFX10-NEXT: global_store_dwordx2 v2, v[0:1], s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: rotr_v2i32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b128 s[0:3], s[4:5], 0x24
; GFX11-NEXT: s_load_b64 s[4:5], s[4:5], 0x34
; GFX11-NEXT: v_mov_b32_e32 v2, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_alignbit_b32 v1, s3, s3, s5
; GFX11-NEXT: v_alignbit_b32 v0, s2, s2, s4
; GFX11-NEXT: global_store_b64 v2, v[0:1], s[0:1]
; GFX11-NEXT: s_endpgm
entry:
%tmp0 = sub <2 x i32> <i32 32, i32 32>, %y
%tmp1 = shl <2 x i32> %x, %tmp0
%tmp2 = lshr <2 x i32> %x, %y
%tmp3 = or <2 x i32> %tmp1, %tmp2
store <2 x i32> %tmp3, ptr addrspace(1) %in
ret void
}
define amdgpu_kernel void @rotr_v4i32(ptr addrspace(1) %in, <4 x i32> %x, <4 x i32> %y) {
; R600-LABEL: rotr_v4i32:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 5, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[4].X, KC0[4].X, KC0[5].X,
; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[3].W, KC0[3].W, KC0[4].W,
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[3].Z, KC0[3].Z, KC0[4].Z,
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[3].Y, KC0[3].Y, KC0[4].Y,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; SI-LABEL: rotr_v4i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0xd
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s15
; SI-NEXT: v_alignbit_b32 v3, s11, s11, v0
; SI-NEXT: v_mov_b32_e32 v0, s14
; SI-NEXT: v_alignbit_b32 v2, s10, s10, v0
; SI-NEXT: v_mov_b32_e32 v0, s13
; SI-NEXT: v_alignbit_b32 v1, s9, s9, v0
; SI-NEXT: v_mov_b32_e32 v0, s12
; SI-NEXT: v_alignbit_b32 v0, s8, s8, v0
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; GFX8-LABEL: rotr_v4i32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v0, s15
; GFX8-NEXT: v_mov_b32_e32 v1, s14
; GFX8-NEXT: v_mov_b32_e32 v4, s13
; GFX8-NEXT: v_alignbit_b32 v3, s11, s11, v0
; GFX8-NEXT: v_alignbit_b32 v2, s10, s10, v1
; GFX8-NEXT: v_alignbit_b32 v1, s9, s9, v4
; GFX8-NEXT: v_mov_b32_e32 v0, s12
; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_alignbit_b32 v0, s8, s8, v0
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
;
; GFX10-LABEL: rotr_v4i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx8 s[8:15], s[4:5], 0x34
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v4, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v3, s11, s11, s15
; GFX10-NEXT: v_alignbit_b32 v2, s10, s10, s14
; GFX10-NEXT: v_alignbit_b32 v1, s9, s9, s13
; GFX10-NEXT: v_alignbit_b32 v0, s8, s8, s12
; GFX10-NEXT: global_store_dwordx4 v4, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: rotr_v4i32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b256 s[8:15], s[4:5], 0x34
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: v_mov_b32_e32 v4, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_alignbit_b32 v3, s11, s11, s15
; GFX11-NEXT: v_alignbit_b32 v2, s10, s10, s14
; GFX11-NEXT: v_alignbit_b32 v1, s9, s9, s13
; GFX11-NEXT: v_alignbit_b32 v0, s8, s8, s12
; GFX11-NEXT: global_store_b128 v4, v[0:3], s[0:1]
; GFX11-NEXT: s_endpgm
entry:
%tmp0 = sub <4 x i32> <i32 32, i32 32, i32 32, i32 32>, %y
%tmp1 = shl <4 x i32> %x, %tmp0
%tmp2 = lshr <4 x i32> %x, %y
%tmp3 = or <4 x i32> %tmp1, %tmp2
store <4 x i32> %tmp3, ptr addrspace(1) %in
ret void
}
define amdgpu_kernel void @rotr_v8i32(ptr addrspace(1) %in, <8 x i32> %x, <8 x i32> %y) {
; R600-LABEL: rotr_v8i32:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 13, @4, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T2.XYZW, T3.X, 0
; R600-NEXT: MEM_RAT_CACHELESS STORE_RAW T0.XYZW, T1.X, 1
; R600-NEXT: CF_END
; R600-NEXT: ALU clause starting at 4:
; R600-NEXT: BIT_ALIGN_INT * T0.W, KC0[5].X, KC0[5].X, KC0[7].X,
; R600-NEXT: BIT_ALIGN_INT * T0.Z, KC0[4].W, KC0[4].W, KC0[6].W,
; R600-NEXT: BIT_ALIGN_INT * T0.Y, KC0[4].Z, KC0[4].Z, KC0[6].Z,
; R600-NEXT: BIT_ALIGN_INT * T0.X, KC0[4].Y, KC0[4].Y, KC0[6].Y,
; R600-NEXT: LSHR * T1.X, KC0[2].Y, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
; R600-NEXT: BIT_ALIGN_INT * T2.W, KC0[6].X, KC0[6].X, KC0[8].X,
; R600-NEXT: BIT_ALIGN_INT * T2.Z, KC0[5].W, KC0[5].W, KC0[7].W,
; R600-NEXT: BIT_ALIGN_INT * T2.Y, KC0[5].Z, KC0[5].Z, KC0[7].Z,
; R600-NEXT: BIT_ALIGN_INT * T2.X, KC0[5].Y, KC0[5].Y, KC0[7].Y,
; R600-NEXT: ADD_INT * T1.W, KC0[2].Y, literal.x,
; R600-NEXT: 16(2.242078e-44), 0(0.000000e+00)
; R600-NEXT: LSHR * T3.X, PV.W, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; SI-LABEL: rotr_v8i32:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x11
; SI-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x9
; SI-NEXT: s_mov_b32 s3, 0xf000
; SI-NEXT: s_mov_b32 s2, -1
; SI-NEXT: s_waitcnt lgkmcnt(0)
; SI-NEXT: v_mov_b32_e32 v0, s19
; SI-NEXT: v_alignbit_b32 v3, s11, s11, v0
; SI-NEXT: v_mov_b32_e32 v0, s18
; SI-NEXT: v_alignbit_b32 v2, s10, s10, v0
; SI-NEXT: v_mov_b32_e32 v0, s17
; SI-NEXT: v_alignbit_b32 v1, s9, s9, v0
; SI-NEXT: v_mov_b32_e32 v0, s16
; SI-NEXT: v_alignbit_b32 v0, s8, s8, v0
; SI-NEXT: v_mov_b32_e32 v4, s23
; SI-NEXT: v_alignbit_b32 v7, s15, s15, v4
; SI-NEXT: v_mov_b32_e32 v4, s22
; SI-NEXT: v_alignbit_b32 v6, s14, s14, v4
; SI-NEXT: v_mov_b32_e32 v4, s21
; SI-NEXT: v_alignbit_b32 v5, s13, s13, v4
; SI-NEXT: v_mov_b32_e32 v4, s20
; SI-NEXT: v_alignbit_b32 v4, s12, s12, v4
; SI-NEXT: buffer_store_dwordx4 v[4:7], off, s[0:3], 0 offset:16
; SI-NEXT: buffer_store_dwordx4 v[0:3], off, s[0:3], 0
; SI-NEXT: s_endpgm
;
; GFX8-LABEL: rotr_v8i32:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44
; GFX8-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX8-NEXT: s_waitcnt lgkmcnt(0)
; GFX8-NEXT: v_mov_b32_e32 v1, s18
; GFX8-NEXT: v_mov_b32_e32 v4, s17
; GFX8-NEXT: v_alignbit_b32 v2, s10, s10, v1
; GFX8-NEXT: v_alignbit_b32 v1, s9, s9, v4
; GFX8-NEXT: v_mov_b32_e32 v4, s23
; GFX8-NEXT: v_alignbit_b32 v7, s15, s15, v4
; GFX8-NEXT: v_mov_b32_e32 v4, s22
; GFX8-NEXT: s_add_u32 s2, s0, 16
; GFX8-NEXT: v_alignbit_b32 v6, s14, s14, v4
; GFX8-NEXT: v_mov_b32_e32 v4, s21
; GFX8-NEXT: s_addc_u32 s3, s1, 0
; GFX8-NEXT: v_alignbit_b32 v5, s13, s13, v4
; GFX8-NEXT: v_mov_b32_e32 v4, s20
; GFX8-NEXT: v_mov_b32_e32 v9, s3
; GFX8-NEXT: v_mov_b32_e32 v0, s19
; GFX8-NEXT: v_alignbit_b32 v4, s12, s12, v4
; GFX8-NEXT: v_mov_b32_e32 v8, s2
; GFX8-NEXT: v_alignbit_b32 v3, s11, s11, v0
; GFX8-NEXT: v_mov_b32_e32 v0, s16
; GFX8-NEXT: flat_store_dwordx4 v[8:9], v[4:7]
; GFX8-NEXT: v_alignbit_b32 v0, s8, s8, v0
; GFX8-NEXT: v_mov_b32_e32 v5, s1
; GFX8-NEXT: v_mov_b32_e32 v4, s0
; GFX8-NEXT: flat_store_dwordx4 v[4:5], v[0:3]
; GFX8-NEXT: s_endpgm
;
; GFX10-LABEL: rotr_v8i32:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_clause 0x1
; GFX10-NEXT: s_load_dwordx16 s[8:23], s[4:5], 0x44
; GFX10-NEXT: s_load_dwordx2 s[0:1], s[4:5], 0x24
; GFX10-NEXT: v_mov_b32_e32 v8, 0
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
; GFX10-NEXT: v_alignbit_b32 v7, s15, s15, s23
; GFX10-NEXT: v_alignbit_b32 v6, s14, s14, s22
; GFX10-NEXT: v_alignbit_b32 v5, s13, s13, s21
; GFX10-NEXT: v_alignbit_b32 v4, s12, s12, s20
; GFX10-NEXT: v_alignbit_b32 v3, s11, s11, s19
; GFX10-NEXT: v_alignbit_b32 v2, s10, s10, s18
; GFX10-NEXT: v_alignbit_b32 v1, s9, s9, s17
; GFX10-NEXT: v_alignbit_b32 v0, s8, s8, s16
; GFX10-NEXT: global_store_dwordx4 v8, v[4:7], s[0:1] offset:16
; GFX10-NEXT: global_store_dwordx4 v8, v[0:3], s[0:1]
; GFX10-NEXT: s_endpgm
;
; GFX11-LABEL: rotr_v8i32:
; GFX11: ; %bb.0: ; %entry
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: s_load_b512 s[8:23], s[4:5], 0x44
; GFX11-NEXT: s_load_b64 s[0:1], s[4:5], 0x24
; GFX11-NEXT: v_mov_b32_e32 v8, 0
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
; GFX11-NEXT: v_alignbit_b32 v7, s15, s15, s23
; GFX11-NEXT: v_alignbit_b32 v6, s14, s14, s22
; GFX11-NEXT: v_alignbit_b32 v5, s13, s13, s21
; GFX11-NEXT: v_alignbit_b32 v4, s12, s12, s20
; GFX11-NEXT: v_alignbit_b32 v3, s11, s11, s19
; GFX11-NEXT: v_alignbit_b32 v2, s10, s10, s18
; GFX11-NEXT: v_alignbit_b32 v1, s9, s9, s17
; GFX11-NEXT: v_alignbit_b32 v0, s8, s8, s16
; GFX11-NEXT: s_clause 0x1
; GFX11-NEXT: global_store_b128 v8, v[4:7], s[0:1] offset:16
; GFX11-NEXT: global_store_b128 v8, v[0:3], s[0:1]
; GFX11-NEXT: s_endpgm
entry:
%tmp0 = sub <8 x i32> <i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32, i32 32>, %y
%tmp1 = shl <8 x i32> %x, %tmp0
%tmp2 = lshr <8 x i32> %x, %y
%tmp3 = or <8 x i32> %tmp1, %tmp2
store <8 x i32> %tmp3, ptr addrspace(1) %in
ret void
}
declare i16 @llvm.fshr.i16(i16, i16, i16)
define void @test_rotr_i16(ptr addrspace(1) nocapture readonly %sourceA, ptr addrspace(1) nocapture readonly %sourceB, ptr addrspace(1) nocapture %destValues) {
; R600-LABEL: test_rotr_i16:
; R600: ; %bb.0: ; %entry
; R600-NEXT: ALU 0, @12, KC0[CB0:0-32], KC1[]
; R600-NEXT: TEX 0 @8
; R600-NEXT: ALU 0, @13, KC0[CB0:0-32], KC1[]
; R600-NEXT: TEX 0 @10
; R600-NEXT: ALU 21, @14, KC0[CB0:0-32], KC1[]
; R600-NEXT: MEM_RAT MSKOR T0.XW, T1.X
; R600-NEXT: CF_END
; R600-NEXT: PAD
; R600-NEXT: Fetch clause starting at 8:
; R600-NEXT: VTX_READ_16 T0.X, T0.X, 48, #1
; R600-NEXT: Fetch clause starting at 10:
; R600-NEXT: VTX_READ_16 T1.X, T1.X, 32, #1
; R600-NEXT: ALU clause starting at 12:
; R600-NEXT: MOV * T0.X, KC0[2].Z,
; R600-NEXT: ALU clause starting at 13:
; R600-NEXT: MOV * T1.X, KC0[2].Y,
; R600-NEXT: ALU clause starting at 14:
; R600-NEXT: SUB_INT T0.W, 0.0, T0.X,
; R600-NEXT: AND_INT * T1.W, T0.X, literal.x,
; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)
; R600-NEXT: AND_INT * T0.W, PV.W, literal.x,
; R600-NEXT: 15(2.101948e-44), 0(0.000000e+00)
; R600-NEXT: LSHL T0.Z, T1.X, PV.W,
; R600-NEXT: LSHR T0.W, T1.X, T1.W,
; R600-NEXT: ADD_INT * T1.W, KC0[2].W, literal.x,
; R600-NEXT: 8(1.121039e-44), 0(0.000000e+00)
; R600-NEXT: AND_INT T2.W, PS, literal.x,
; R600-NEXT: OR_INT * T0.W, PV.W, PV.Z,
; R600-NEXT: 3(4.203895e-45), 0(0.000000e+00)
; R600-NEXT: AND_INT T0.W, PS, literal.x,
; R600-NEXT: LSHL * T2.W, PV.W, literal.y,
; R600-NEXT: 65535(9.183409e-41), 3(4.203895e-45)
; R600-NEXT: LSHL T0.X, PV.W, PS,
; R600-NEXT: LSHL * T0.W, literal.x, PS,
; R600-NEXT: 65535(9.183409e-41), 0(0.000000e+00)
; R600-NEXT: MOV T0.Y, 0.0,
; R600-NEXT: MOV * T0.Z, 0.0,
; R600-NEXT: LSHR * T1.X, T1.W, literal.x,
; R600-NEXT: 2(2.802597e-45), 0(0.000000e+00)
;
; SI-LABEL: test_rotr_i16:
; SI: ; %bb.0: ; %entry
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; SI-NEXT: s_mov_b32 s6, 0
; SI-NEXT: s_mov_b32 s7, 0xf000
; SI-NEXT: s_mov_b32 s4, s6
; SI-NEXT: s_mov_b32 s5, s6
; SI-NEXT: buffer_load_ushort v2, v[2:3], s[4:7], 0 addr64 offset:48
; SI-NEXT: buffer_load_ushort v0, v[0:1], s[4:7], 0 addr64 offset:32
; SI-NEXT: s_waitcnt vmcnt(1)
; SI-NEXT: v_and_b32_e32 v1, 15, v2
; SI-NEXT: v_sub_i32_e32 v2, vcc, 0, v2
; SI-NEXT: s_waitcnt vmcnt(0)
; SI-NEXT: v_lshrrev_b32_e32 v1, v1, v0
; SI-NEXT: v_and_b32_e32 v2, 15, v2
; SI-NEXT: v_lshlrev_b32_e32 v0, v2, v0
; SI-NEXT: v_or_b32_e32 v0, v1, v0
; SI-NEXT: buffer_store_short v0, v[4:5], s[4:7], 0 addr64 offset:8
; SI-NEXT: s_waitcnt vmcnt(0) expcnt(0)
; SI-NEXT: s_setpc_b64 s[30:31]
;
; GFX8-LABEL: test_rotr_i16:
; GFX8: ; %bb.0: ; %entry
; GFX8-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 32, v0
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
; GFX8-NEXT: v_add_u32_e32 v2, vcc, 48, v2
; GFX8-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
; GFX8-NEXT: flat_load_ushort v2, v[2:3]
; GFX8-NEXT: flat_load_ushort v0, v[0:1]
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: v_lshrrev_b16_e32 v1, v2, v0
; GFX8-NEXT: v_sub_u16_e32 v2, 0, v2
; GFX8-NEXT: v_lshlrev_b16_e32 v0, v2, v0
; GFX8-NEXT: v_or_b32_e32 v2, v1, v0
; GFX8-NEXT: v_add_u32_e32 v0, vcc, 8, v4
; GFX8-NEXT: v_addc_u32_e32 v1, vcc, 0, v5, vcc
; GFX8-NEXT: flat_store_short v[0:1], v2
; GFX8-NEXT: s_waitcnt vmcnt(0)
; GFX8-NEXT: s_setpc_b64 s[30:31]
;
; GFX10-LABEL: test_rotr_i16:
; GFX10: ; %bb.0: ; %entry
; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX10-NEXT: global_load_ushort v6, v[2:3], off offset:48
; GFX10-NEXT: global_load_ushort v7, v[0:1], off offset:32
; GFX10-NEXT: s_waitcnt vmcnt(1)
; GFX10-NEXT: v_sub_nc_u16 v0, 0, v6
; GFX10-NEXT: s_waitcnt vmcnt(0)
; GFX10-NEXT: v_lshrrev_b16 v1, v6, v7
; GFX10-NEXT: v_lshlrev_b16 v0, v0, v7
; GFX10-NEXT: v_or_b32_e32 v0, v1, v0
; GFX10-NEXT: global_store_short v[4:5], v0, off offset:8
; GFX10-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-TRUE16-LABEL: test_rotr_i16:
; GFX11-TRUE16: ; %bb.0: ; %entry
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-TRUE16-NEXT: global_load_d16_b16 v2, v[2:3], off offset:48
; GFX11-TRUE16-NEXT: global_load_d16_b16 v0, v[0:1], off offset:32
; GFX11-TRUE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-TRUE16-NEXT: v_sub_nc_u16 v0.h, 0, v2.l
; GFX11-TRUE16-NEXT: v_lshrrev_b16 v1.l, v2.l, v0.l
; GFX11-TRUE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-TRUE16-NEXT: v_lshlrev_b16 v0.l, v0.h, v0.l
; GFX11-TRUE16-NEXT: v_or_b16 v0.l, v1.l, v0.l
; GFX11-TRUE16-NEXT: global_store_b16 v[4:5], v0, off offset:8
; GFX11-TRUE16-NEXT: s_setpc_b64 s[30:31]
;
; GFX11-FAKE16-LABEL: test_rotr_i16:
; GFX11-FAKE16: ; %bb.0: ; %entry
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
; GFX11-FAKE16-NEXT: global_load_u16 v2, v[2:3], off offset:48
; GFX11-FAKE16-NEXT: global_load_u16 v0, v[0:1], off offset:32
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(1)
; GFX11-FAKE16-NEXT: v_sub_nc_u16 v1, 0, v2
; GFX11-FAKE16-NEXT: s_waitcnt vmcnt(0)
; GFX11-FAKE16-NEXT: v_lshrrev_b16 v2, v2, v0
; GFX11-FAKE16-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
; GFX11-FAKE16-NEXT: v_lshlrev_b16 v0, v1, v0
; GFX11-FAKE16-NEXT: v_or_b32_e32 v0, v2, v0
; GFX11-FAKE16-NEXT: global_store_b16 v[4:5], v0, off offset:8
; GFX11-FAKE16-NEXT: s_setpc_b64 s[30:31]
entry:
%arrayidx = getelementptr inbounds i16, ptr addrspace(1) %sourceA, i64 16
%a = load i16, ptr addrspace(1) %arrayidx
%arrayidx2 = getelementptr inbounds i16, ptr addrspace(1) %sourceB, i64 24
%b = load i16, ptr addrspace(1) %arrayidx2
%c = tail call i16 @llvm.fshr.i16(i16 %a, i16 %a, i16 %b)
%arrayidx5 = getelementptr inbounds i16, ptr addrspace(1) %destValues, i64 4
store i16 %c, ptr addrspace(1) %arrayidx5
ret void
}
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