49b492048a
Consistently treat packed 16-bit operands as 32-bit values, because that's really what they are. The attempt to treat them differently was ultimately incorrect and lead to miscompiles, e.g. when using non-splat constants such as (1, 0) as operands. Recognize 32-bit float constants for i/u16 instructions. This is a bit odd conceptually, but it matches HW behavior and SP3. Remove isFoldableLiteralV216; there was too much magic in the dependency between it and its use in SIFoldOperands. Instead, we now simply rely on checking whether a constant is an inline constant, and trying a bunch of permutations of the low and high halves. This is more obviously correct and leads to some new cases where inline constants are used as shown by tests. Move the logic for switching packed add vs. sub into SIFoldOperands. This has two benefits: all logic that optimizes for inline constants in packed math is now in one place; and it applies to both SelectionDAG and GISel paths. Disable the use of opsel with v_dot* instructions on gfx11. They are documented to ignore opsel on src0 and src1. It may be interesting to re-enable to use of opsel on src2 as a future optimization. A similar "proper" fix of what inline constants mean could potentially be applied to unpacked 16-bit ops. However, it's less clear what the benefit would be, and there are surely places where we'd have to carefully audit whether values are properly sign- or zero-extended. It is best to keep such a change separate. Fixes: Corruption in FSR 2.0 (latent bug exposed by an LLPC change)
627 lines
21 KiB
C++
627 lines
21 KiB
C++
//===-- AMDGPUMCCodeEmitter.cpp - AMDGPU Code Emitter ---------------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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/// \file
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/// The AMDGPU code emitter produces machine code that can be executed
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/// directly on the GPU device.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/AMDGPUFixupKinds.h"
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#include "MCTargetDesc/AMDGPUMCTargetDesc.h"
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#include "SIDefines.h"
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#include "Utils/AMDGPUBaseInfo.h"
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#include "llvm/ADT/APInt.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/TargetParser/SubtargetFeature.h"
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#include <optional>
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using namespace llvm;
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namespace {
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class AMDGPUMCCodeEmitter : public MCCodeEmitter {
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const MCRegisterInfo &MRI;
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const MCInstrInfo &MCII;
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public:
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AMDGPUMCCodeEmitter(const MCInstrInfo &MCII, const MCRegisterInfo &MRI)
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: MRI(MRI), MCII(MCII) {}
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/// Encode the instruction and write it to the OS.
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void encodeInstruction(const MCInst &MI, SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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void getMachineOpValue(const MCInst &MI, const MCOperand &MO, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void getMachineOpValueT16(const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void getMachineOpValueT16Lo128(const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Use a fixup to encode the simm16 field for SOPP branch
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/// instructions.
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void getSOPPBrEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void getSMEMOffsetEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void getSDWASrcEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void getSDWAVopcDstEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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void getAVOperandEncoding(const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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private:
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uint64_t getImplicitOpSelHiEncoding(int Opcode) const;
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void getMachineOpValueCommon(const MCInst &MI, const MCOperand &MO,
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unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Encode an fp or int literal.
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std::optional<uint32_t> getLitEncoding(const MCOperand &MO,
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const MCOperandInfo &OpInfo,
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const MCSubtargetInfo &STI) const;
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void getBinaryCodeForInstr(const MCInst &MI, SmallVectorImpl<MCFixup> &Fixups,
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APInt &Inst, APInt &Scratch,
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const MCSubtargetInfo &STI) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createAMDGPUMCCodeEmitter(const MCInstrInfo &MCII,
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MCContext &Ctx) {
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return new AMDGPUMCCodeEmitter(MCII, *Ctx.getRegisterInfo());
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}
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// Returns the encoding value to use if the given integer is an integer inline
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// immediate value, or 0 if it is not.
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template <typename IntTy>
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static uint32_t getIntInlineImmEncoding(IntTy Imm) {
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if (Imm >= 0 && Imm <= 64)
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return 128 + Imm;
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if (Imm >= -16 && Imm <= -1)
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return 192 + std::abs(Imm);
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return 0;
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}
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static uint32_t getLit16IntEncoding(uint16_t Val, const MCSubtargetInfo &STI) {
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uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
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return IntImm == 0 ? 255 : IntImm;
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}
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static uint32_t getLit16Encoding(uint16_t Val, const MCSubtargetInfo &STI) {
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uint16_t IntImm = getIntInlineImmEncoding(static_cast<int16_t>(Val));
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if (IntImm != 0)
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return IntImm;
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if (Val == 0x3800) // 0.5
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return 240;
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if (Val == 0xB800) // -0.5
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return 241;
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if (Val == 0x3C00) // 1.0
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return 242;
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if (Val == 0xBC00) // -1.0
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return 243;
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if (Val == 0x4000) // 2.0
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return 244;
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if (Val == 0xC000) // -2.0
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return 245;
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if (Val == 0x4400) // 4.0
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return 246;
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if (Val == 0xC400) // -4.0
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return 247;
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if (Val == 0x3118 && // 1.0 / (2.0 * pi)
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STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
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return 248;
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return 255;
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}
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static uint32_t getLit32Encoding(uint32_t Val, const MCSubtargetInfo &STI) {
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uint32_t IntImm = getIntInlineImmEncoding(static_cast<int32_t>(Val));
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if (IntImm != 0)
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return IntImm;
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if (Val == llvm::bit_cast<uint32_t>(0.5f))
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return 240;
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if (Val == llvm::bit_cast<uint32_t>(-0.5f))
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return 241;
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if (Val == llvm::bit_cast<uint32_t>(1.0f))
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return 242;
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if (Val == llvm::bit_cast<uint32_t>(-1.0f))
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return 243;
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if (Val == llvm::bit_cast<uint32_t>(2.0f))
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return 244;
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if (Val == llvm::bit_cast<uint32_t>(-2.0f))
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return 245;
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if (Val == llvm::bit_cast<uint32_t>(4.0f))
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return 246;
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if (Val == llvm::bit_cast<uint32_t>(-4.0f))
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return 247;
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if (Val == 0x3e22f983 && // 1.0 / (2.0 * pi)
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STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
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return 248;
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return 255;
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}
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static uint32_t getLit64Encoding(uint64_t Val, const MCSubtargetInfo &STI) {
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uint32_t IntImm = getIntInlineImmEncoding(static_cast<int64_t>(Val));
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if (IntImm != 0)
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return IntImm;
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if (Val == llvm::bit_cast<uint64_t>(0.5))
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return 240;
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if (Val == llvm::bit_cast<uint64_t>(-0.5))
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return 241;
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if (Val == llvm::bit_cast<uint64_t>(1.0))
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return 242;
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if (Val == llvm::bit_cast<uint64_t>(-1.0))
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return 243;
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if (Val == llvm::bit_cast<uint64_t>(2.0))
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return 244;
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if (Val == llvm::bit_cast<uint64_t>(-2.0))
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return 245;
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if (Val == llvm::bit_cast<uint64_t>(4.0))
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return 246;
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if (Val == llvm::bit_cast<uint64_t>(-4.0))
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return 247;
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if (Val == 0x3fc45f306dc9c882 && // 1.0 / (2.0 * pi)
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STI.hasFeature(AMDGPU::FeatureInv2PiInlineImm))
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return 248;
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return 255;
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}
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std::optional<uint32_t>
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AMDGPUMCCodeEmitter::getLitEncoding(const MCOperand &MO,
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const MCOperandInfo &OpInfo,
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const MCSubtargetInfo &STI) const {
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int64_t Imm;
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if (MO.isExpr()) {
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const auto *C = dyn_cast<MCConstantExpr>(MO.getExpr());
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if (!C)
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return 255;
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Imm = C->getValue();
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} else {
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assert(!MO.isDFPImm());
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if (!MO.isImm())
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return {};
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Imm = MO.getImm();
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}
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switch (OpInfo.OperandType) {
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case AMDGPU::OPERAND_REG_IMM_INT32:
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case AMDGPU::OPERAND_REG_IMM_FP32:
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case AMDGPU::OPERAND_REG_IMM_FP32_DEFERRED:
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case AMDGPU::OPERAND_REG_INLINE_C_INT32:
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case AMDGPU::OPERAND_REG_INLINE_C_FP32:
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case AMDGPU::OPERAND_REG_INLINE_AC_INT32:
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case AMDGPU::OPERAND_REG_INLINE_AC_FP32:
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case AMDGPU::OPERAND_REG_IMM_V2INT32:
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case AMDGPU::OPERAND_REG_IMM_V2FP32:
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case AMDGPU::OPERAND_REG_INLINE_C_V2INT32:
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case AMDGPU::OPERAND_REG_INLINE_C_V2FP32:
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case AMDGPU::OPERAND_INLINE_SPLIT_BARRIER_INT32:
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return getLit32Encoding(static_cast<uint32_t>(Imm), STI);
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case AMDGPU::OPERAND_REG_IMM_INT64:
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case AMDGPU::OPERAND_REG_IMM_FP64:
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case AMDGPU::OPERAND_REG_INLINE_C_INT64:
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case AMDGPU::OPERAND_REG_INLINE_C_FP64:
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case AMDGPU::OPERAND_REG_INLINE_AC_FP64:
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return getLit64Encoding(static_cast<uint64_t>(Imm), STI);
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case AMDGPU::OPERAND_REG_IMM_INT16:
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case AMDGPU::OPERAND_REG_INLINE_C_INT16:
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case AMDGPU::OPERAND_REG_INLINE_AC_INT16:
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return getLit16IntEncoding(static_cast<uint16_t>(Imm), STI);
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case AMDGPU::OPERAND_REG_IMM_FP16:
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case AMDGPU::OPERAND_REG_IMM_FP16_DEFERRED:
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case AMDGPU::OPERAND_REG_INLINE_C_FP16:
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case AMDGPU::OPERAND_REG_INLINE_AC_FP16:
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// FIXME Is this correct? What do inline immediates do on SI for f16 src
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// which does not have f16 support?
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return getLit16Encoding(static_cast<uint16_t>(Imm), STI);
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case AMDGPU::OPERAND_REG_IMM_V2INT16:
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case AMDGPU::OPERAND_REG_INLINE_C_V2INT16:
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case AMDGPU::OPERAND_REG_INLINE_AC_V2INT16:
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return AMDGPU::getInlineEncodingV2I16(static_cast<uint32_t>(Imm))
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.value_or(255);
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case AMDGPU::OPERAND_REG_IMM_V2FP16:
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case AMDGPU::OPERAND_REG_INLINE_C_V2FP16:
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case AMDGPU::OPERAND_REG_INLINE_AC_V2FP16:
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return AMDGPU::getInlineEncodingV2F16(static_cast<uint32_t>(Imm))
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.value_or(255);
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case AMDGPU::OPERAND_KIMM32:
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case AMDGPU::OPERAND_KIMM16:
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return MO.getImm();
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default:
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llvm_unreachable("invalid operand size");
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}
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}
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uint64_t AMDGPUMCCodeEmitter::getImplicitOpSelHiEncoding(int Opcode) const {
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using namespace AMDGPU::VOP3PEncoding;
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using namespace AMDGPU::OpName;
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if (AMDGPU::hasNamedOperand(Opcode, op_sel_hi)) {
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if (AMDGPU::hasNamedOperand(Opcode, src2))
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return 0;
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if (AMDGPU::hasNamedOperand(Opcode, src1))
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return OP_SEL_HI_2;
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if (AMDGPU::hasNamedOperand(Opcode, src0))
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return OP_SEL_HI_1 | OP_SEL_HI_2;
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}
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return OP_SEL_HI_0 | OP_SEL_HI_1 | OP_SEL_HI_2;
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}
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static bool isVCMPX64(const MCInstrDesc &Desc) {
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return (Desc.TSFlags & SIInstrFlags::VOP3) &&
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Desc.hasImplicitDefOfPhysReg(AMDGPU::EXEC);
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}
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void AMDGPUMCCodeEmitter::encodeInstruction(const MCInst &MI,
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SmallVectorImpl<char> &CB,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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int Opcode = MI.getOpcode();
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APInt Encoding, Scratch;
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getBinaryCodeForInstr(MI, Fixups, Encoding, Scratch, STI);
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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unsigned bytes = Desc.getSize();
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// Set unused op_sel_hi bits to 1 for VOP3P and MAI instructions.
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// Note that accvgpr_read/write are MAI, have src0, but do not use op_sel.
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if ((Desc.TSFlags & SIInstrFlags::VOP3P) ||
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Opcode == AMDGPU::V_ACCVGPR_READ_B32_vi ||
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Opcode == AMDGPU::V_ACCVGPR_WRITE_B32_vi) {
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Encoding |= getImplicitOpSelHiEncoding(Opcode);
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}
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// GFX10+ v_cmpx opcodes promoted to VOP3 have implied dst=EXEC.
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// Documentation requires dst to be encoded as EXEC (0x7E),
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// but it looks like the actual value encoded for dst operand
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// is ignored by HW. It was decided to define dst as "do not care"
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// in td files to allow disassembler accept any dst value.
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// However, dst is encoded as EXEC for compatibility with SP3.
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if (AMDGPU::isGFX10Plus(STI) && isVCMPX64(Desc)) {
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assert((Encoding & 0xFF) == 0);
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Encoding |= MRI.getEncodingValue(AMDGPU::EXEC_LO) &
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AMDGPU::HWEncoding::REG_IDX_MASK;
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}
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for (unsigned i = 0; i < bytes; i++) {
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CB.push_back((uint8_t)Encoding.extractBitsAsZExtValue(8, 8 * i));
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}
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// NSA encoding.
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if (AMDGPU::isGFX10Plus(STI) && Desc.TSFlags & SIInstrFlags::MIMG) {
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int vaddr0 = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
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AMDGPU::OpName::vaddr0);
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int srsrc = AMDGPU::getNamedOperandIdx(MI.getOpcode(),
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AMDGPU::OpName::srsrc);
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assert(vaddr0 >= 0 && srsrc > vaddr0);
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unsigned NumExtraAddrs = srsrc - vaddr0 - 1;
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unsigned NumPadding = (-NumExtraAddrs) & 3;
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for (unsigned i = 0; i < NumExtraAddrs; ++i) {
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getMachineOpValue(MI, MI.getOperand(vaddr0 + 1 + i), Encoding, Fixups,
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STI);
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CB.push_back((uint8_t)Encoding.getLimitedValue());
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}
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CB.append(NumPadding, 0);
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}
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if ((bytes > 8 && STI.hasFeature(AMDGPU::FeatureVOP3Literal)) ||
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(bytes > 4 && !STI.hasFeature(AMDGPU::FeatureVOP3Literal)))
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return;
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// Do not print literals from SISrc Operands for insts with mandatory literals
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if (AMDGPU::hasNamedOperand(MI.getOpcode(), AMDGPU::OpName::imm))
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return;
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// Check for additional literals
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for (unsigned i = 0, e = Desc.getNumOperands(); i < e; ++i) {
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// Check if this operand should be encoded as [SV]Src
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if (!AMDGPU::isSISrcOperand(Desc, i))
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continue;
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// Is this operand a literal immediate?
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const MCOperand &Op = MI.getOperand(i);
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auto Enc = getLitEncoding(Op, Desc.operands()[i], STI);
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if (!Enc || *Enc != 255)
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continue;
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// Yes! Encode it
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int64_t Imm = 0;
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if (Op.isImm())
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Imm = Op.getImm();
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else if (Op.isExpr()) {
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if (const auto *C = dyn_cast<MCConstantExpr>(Op.getExpr()))
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Imm = C->getValue();
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} else if (!Op.isExpr()) // Exprs will be replaced with a fixup value.
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llvm_unreachable("Must be immediate or expr");
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if (Desc.operands()[i].OperandType == AMDGPU::OPERAND_REG_IMM_FP64)
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Imm = Hi_32(Imm);
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support::endian::write<uint32_t>(CB, Imm, llvm::endianness::little);
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// Only one literal value allowed
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break;
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}
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}
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void AMDGPUMCCodeEmitter::getSOPPBrEncoding(const MCInst &MI, unsigned OpNo,
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APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isExpr()) {
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const MCExpr *Expr = MO.getExpr();
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MCFixupKind Kind = (MCFixupKind)AMDGPU::fixup_si_sopp_br;
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Fixups.push_back(MCFixup::create(0, Expr, Kind, MI.getLoc()));
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Op = APInt::getZero(96);
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} else {
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getMachineOpValue(MI, MO, Op, Fixups, STI);
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}
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}
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void AMDGPUMCCodeEmitter::getSMEMOffsetEncoding(
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const MCInst &MI, unsigned OpNo, APInt &Op,
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SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
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auto Offset = MI.getOperand(OpNo).getImm();
|
|
// VI only supports 20-bit unsigned offsets.
|
|
assert(!AMDGPU::isVI(STI) || isUInt<20>(Offset));
|
|
Op = Offset;
|
|
}
|
|
|
|
void AMDGPUMCCodeEmitter::getSDWASrcEncoding(const MCInst &MI, unsigned OpNo,
|
|
APInt &Op,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
using namespace AMDGPU::SDWA;
|
|
|
|
uint64_t RegEnc = 0;
|
|
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
|
|
if (MO.isReg()) {
|
|
unsigned Reg = MO.getReg();
|
|
RegEnc |= MRI.getEncodingValue(Reg);
|
|
RegEnc &= SDWA9EncValues::SRC_VGPR_MASK;
|
|
if (AMDGPU::isSGPR(AMDGPU::mc2PseudoReg(Reg), &MRI)) {
|
|
RegEnc |= SDWA9EncValues::SRC_SGPR_MASK;
|
|
}
|
|
Op = RegEnc;
|
|
return;
|
|
} else {
|
|
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
|
|
auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI);
|
|
if (Enc && *Enc != 255) {
|
|
Op = *Enc | SDWA9EncValues::SRC_SGPR_MASK;
|
|
return;
|
|
}
|
|
}
|
|
|
|
llvm_unreachable("Unsupported operand kind");
|
|
}
|
|
|
|
void AMDGPUMCCodeEmitter::getSDWAVopcDstEncoding(
|
|
const MCInst &MI, unsigned OpNo, APInt &Op,
|
|
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
|
|
using namespace AMDGPU::SDWA;
|
|
|
|
uint64_t RegEnc = 0;
|
|
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
|
|
unsigned Reg = MO.getReg();
|
|
if (Reg != AMDGPU::VCC && Reg != AMDGPU::VCC_LO) {
|
|
RegEnc |= MRI.getEncodingValue(Reg);
|
|
RegEnc &= SDWA9EncValues::VOPC_DST_SGPR_MASK;
|
|
RegEnc |= SDWA9EncValues::VOPC_DST_VCC_MASK;
|
|
}
|
|
Op = RegEnc;
|
|
}
|
|
|
|
void AMDGPUMCCodeEmitter::getAVOperandEncoding(
|
|
const MCInst &MI, unsigned OpNo, APInt &Op,
|
|
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
|
|
unsigned Reg = MI.getOperand(OpNo).getReg();
|
|
unsigned Enc = MRI.getEncodingValue(Reg);
|
|
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
|
|
bool IsVGPROrAGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;
|
|
|
|
// VGPR and AGPR have the same encoding, but SrcA and SrcB operands of mfma
|
|
// instructions use acc[0:1] modifier bits to distinguish. These bits are
|
|
// encoded as a virtual 9th bit of the register for these operands.
|
|
bool IsAGPR = false;
|
|
if (MRI.getRegClass(AMDGPU::AGPR_32RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_64RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_96RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_128RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_160RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_192RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_224RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_256RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_288RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_320RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_352RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_384RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AReg_512RegClassID).contains(Reg) ||
|
|
MRI.getRegClass(AMDGPU::AGPR_LO16RegClassID).contains(Reg))
|
|
IsAGPR = true;
|
|
|
|
Op = Idx | (IsVGPROrAGPR << 8) | (IsAGPR << 9);
|
|
}
|
|
|
|
static bool needsPCRel(const MCExpr *Expr) {
|
|
switch (Expr->getKind()) {
|
|
case MCExpr::SymbolRef: {
|
|
auto *SE = cast<MCSymbolRefExpr>(Expr);
|
|
MCSymbolRefExpr::VariantKind Kind = SE->getKind();
|
|
return Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_LO &&
|
|
Kind != MCSymbolRefExpr::VK_AMDGPU_ABS32_HI;
|
|
}
|
|
case MCExpr::Binary: {
|
|
auto *BE = cast<MCBinaryExpr>(Expr);
|
|
if (BE->getOpcode() == MCBinaryExpr::Sub)
|
|
return false;
|
|
return needsPCRel(BE->getLHS()) || needsPCRel(BE->getRHS());
|
|
}
|
|
case MCExpr::Unary:
|
|
return needsPCRel(cast<MCUnaryExpr>(Expr)->getSubExpr());
|
|
case MCExpr::Target:
|
|
case MCExpr::Constant:
|
|
return false;
|
|
}
|
|
llvm_unreachable("invalid kind");
|
|
}
|
|
|
|
void AMDGPUMCCodeEmitter::getMachineOpValue(const MCInst &MI,
|
|
const MCOperand &MO, APInt &Op,
|
|
SmallVectorImpl<MCFixup> &Fixups,
|
|
const MCSubtargetInfo &STI) const {
|
|
if (MO.isReg()){
|
|
unsigned Enc = MRI.getEncodingValue(MO.getReg());
|
|
unsigned Idx = Enc & AMDGPU::HWEncoding::REG_IDX_MASK;
|
|
bool IsVGPR = Enc & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;
|
|
Op = Idx | (IsVGPR << 8);
|
|
return;
|
|
}
|
|
unsigned OpNo = &MO - MI.begin();
|
|
getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
|
|
}
|
|
|
|
void AMDGPUMCCodeEmitter::getMachineOpValueT16(
|
|
const MCInst &MI, unsigned OpNo, APInt &Op,
|
|
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
|
|
llvm_unreachable("TODO: Implement getMachineOpValueT16().");
|
|
}
|
|
|
|
void AMDGPUMCCodeEmitter::getMachineOpValueT16Lo128(
|
|
const MCInst &MI, unsigned OpNo, APInt &Op,
|
|
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
|
|
const MCOperand &MO = MI.getOperand(OpNo);
|
|
if (MO.isReg()) {
|
|
uint16_t Encoding = MRI.getEncodingValue(MO.getReg());
|
|
unsigned RegIdx = Encoding & AMDGPU::HWEncoding::REG_IDX_MASK;
|
|
bool IsHi = Encoding & AMDGPU::HWEncoding::IS_HI;
|
|
bool IsVGPR = Encoding & AMDGPU::HWEncoding::IS_VGPR_OR_AGPR;
|
|
assert((!IsVGPR || isUInt<7>(RegIdx)) && "VGPR0-VGPR127 expected!");
|
|
Op = (IsVGPR ? 0x100 : 0) | (IsHi ? 0x80 : 0) | RegIdx;
|
|
return;
|
|
}
|
|
getMachineOpValueCommon(MI, MO, OpNo, Op, Fixups, STI);
|
|
}
|
|
|
|
void AMDGPUMCCodeEmitter::getMachineOpValueCommon(
|
|
const MCInst &MI, const MCOperand &MO, unsigned OpNo, APInt &Op,
|
|
SmallVectorImpl<MCFixup> &Fixups, const MCSubtargetInfo &STI) const {
|
|
|
|
if (MO.isExpr() && MO.getExpr()->getKind() != MCExpr::Constant) {
|
|
// FIXME: If this is expression is PCRel or not should not depend on what
|
|
// the expression looks like. Given that this is just a general expression,
|
|
// it should probably be FK_Data_4 and whatever is producing
|
|
//
|
|
// s_add_u32 s2, s2, (extern_const_addrspace+16
|
|
//
|
|
// And expecting a PCRel should instead produce
|
|
//
|
|
// .Ltmp1:
|
|
// s_add_u32 s2, s2, (extern_const_addrspace+16)-.Ltmp1
|
|
MCFixupKind Kind;
|
|
if (needsPCRel(MO.getExpr()))
|
|
Kind = FK_PCRel_4;
|
|
else
|
|
Kind = FK_Data_4;
|
|
|
|
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
|
|
uint32_t Offset = Desc.getSize();
|
|
assert(Offset == 4 || Offset == 8);
|
|
|
|
Fixups.push_back(MCFixup::create(Offset, MO.getExpr(), Kind, MI.getLoc()));
|
|
}
|
|
|
|
const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
|
|
if (AMDGPU::isSISrcOperand(Desc, OpNo)) {
|
|
if (auto Enc = getLitEncoding(MO, Desc.operands()[OpNo], STI)) {
|
|
Op = *Enc;
|
|
return;
|
|
}
|
|
} else if (MO.isImm()) {
|
|
Op = MO.getImm();
|
|
return;
|
|
}
|
|
|
|
llvm_unreachable("Encoding of this operand type is not supported yet.");
|
|
}
|
|
|
|
#include "AMDGPUGenMCCodeEmitter.inc"
|