49b492048a
Consistently treat packed 16-bit operands as 32-bit values, because that's really what they are. The attempt to treat them differently was ultimately incorrect and lead to miscompiles, e.g. when using non-splat constants such as (1, 0) as operands. Recognize 32-bit float constants for i/u16 instructions. This is a bit odd conceptually, but it matches HW behavior and SP3. Remove isFoldableLiteralV216; there was too much magic in the dependency between it and its use in SIFoldOperands. Instead, we now simply rely on checking whether a constant is an inline constant, and trying a bunch of permutations of the low and high halves. This is more obviously correct and leads to some new cases where inline constants are used as shown by tests. Move the logic for switching packed add vs. sub into SIFoldOperands. This has two benefits: all logic that optimizes for inline constants in packed math is now in one place; and it applies to both SelectionDAG and GISel paths. Disable the use of opsel with v_dot* instructions on gfx11. They are documented to ignore opsel on src0 and src1. It may be interesting to re-enable to use of opsel on src2 as a future optimization. A similar "proper" fix of what inline constants mean could potentially be applied to unpacked 16-bit ops. However, it's less clear what the benefit would be, and there are surely places where we'd have to carefully audit whether values are properly sign- or zero-extended. It is best to keep such a change separate. Fixes: Corruption in FSR 2.0 (latent bug exposed by an LLPC change)
318 lines
14 KiB
LLVM
318 lines
14 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX9,GFX9-SDAG
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; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx900 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX9,GFX9-GISEL
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; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX10,GFX10-SDAG
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; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1010 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX10,GFX10-GISEL
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; RUN: llc -global-isel=0 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-SDAG
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; RUN: llc -global-isel=1 -march=amdgcn -mcpu=gfx1100 -verify-machineinstrs < %s | FileCheck %s -check-prefixes=GFX11,GFX11-GISEL
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declare half @llvm.fma.f16(half, half, half)
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declare half @llvm.maxnum.f16(half, half)
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define half @test_fma(half %x, half %y, half %z) {
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; GFX9-LABEL: test_fma:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_fma_f16 v0, v0, v1, v2
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: test_fma:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_fma_f16 v0, v0, v1, v2
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: test_fma:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_fma_f16 v0, v0, v1, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%r = call half @llvm.fma.f16(half %x, half %y, half %z)
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ret half %r
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}
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; GFX10+ has v_fmac_f16.
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define half @test_fmac(half %x, half %y, half %z) {
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; GFX9-LABEL: test_fmac:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-NEXT: v_fma_f16 v0, v1, v2, v0
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; GFX9-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: test_fmac:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_fmac_f16_e32 v0, v1, v2
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: test_fmac:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_fmac_f16_e32 v0, v1, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%r = call half @llvm.fma.f16(half %y, half %z, half %x)
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ret half %r
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}
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; GFX10+ has v_fmaak_f16.
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define half @test_fmaak(half %x, half %y, half %z) {
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; GFX9-SDAG-LABEL: test_fmaak:
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; GFX9-SDAG: ; %bb.0:
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; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x4200
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; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, v1, s4
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; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-GISEL-LABEL: test_fmaak:
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; GFX9-GISEL: ; %bb.0:
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; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x4200
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; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, v1, v2
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; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: test_fmaak:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_fmaak_f16 v0, v0, v1, 0x4200
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: test_fmaak:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_fmaak_f16 v0, v0, v1, 0x4200
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%r = call half @llvm.fma.f16(half %x, half %y, half 0xH4200)
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ret half %r
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}
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; GFX10+ has v_fmamk_f16.
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define half @test_fmamk(half %x, half %y, half %z) {
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; GFX9-SDAG-LABEL: test_fmamk:
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; GFX9-SDAG: ; %bb.0:
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; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x4200
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; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, s4, v2
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; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-GISEL-LABEL: test_fmamk:
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; GFX9-GISEL: ; %bb.0:
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; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x4200
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; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, v1, v2
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; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-LABEL: test_fmamk:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-NEXT: v_fmamk_f16 v0, v0, 0x4200, v2
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; GFX10-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-LABEL: test_fmamk:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-NEXT: v_fmamk_f16 v0, v0, 0x4200, v2
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; GFX11-NEXT: s_setpc_b64 s[30:31]
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%r = call half @llvm.fma.f16(half %x, half 0xH4200, half %z)
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ret half %r
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}
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; Regression test for a crash caused by D139469.
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define i32 @test_D139469_f16(half %arg) {
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; GFX9-SDAG-LABEL: test_D139469_f16:
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; GFX9-SDAG: ; %bb.0: ; %bb
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; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x291e
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; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x211e
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; GFX9-SDAG-NEXT: v_mul_f16_e32 v1, 0x291e, v0
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; GFX9-SDAG-NEXT: v_fma_f16 v0, v0, s4, v2
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; GFX9-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
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; GFX9-SDAG-NEXT: v_cmp_gt_f16_e32 vcc, 0, v0
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; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-GISEL-LABEL: test_D139469_f16:
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; GFX9-GISEL: ; %bb.0: ; %bb
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; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-GISEL-NEXT: v_mul_f16_e32 v2, 0x291e, v0
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x291e
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; GFX9-GISEL-NEXT: v_cmp_gt_f16_e32 vcc, 0, v2
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x211e
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; GFX9-GISEL-NEXT: v_fma_f16 v0, v0, v1, v2
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; GFX9-GISEL-NEXT: v_cmp_gt_f16_e64 s[4:5], 0, v0
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; GFX9-GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
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; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
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; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-SDAG-LABEL: test_D139469_f16:
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; GFX10-SDAG: ; %bb.0: ; %bb
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; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x291e
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; GFX10-SDAG-NEXT: v_mul_f16_e32 v1, 0x291e, v0
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; GFX10-SDAG-NEXT: v_fmaak_f16 v0, s4, v0, 0x211e
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; GFX10-SDAG-NEXT: v_min_f16_e32 v0, v1, v0
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; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
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; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
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; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-GISEL-LABEL: test_D139469_f16:
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; GFX10-GISEL: ; %bb.0: ; %bb
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; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0x211e
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; GFX10-GISEL-NEXT: v_mul_f16_e32 v2, 0x291e, v0
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; GFX10-GISEL-NEXT: v_fmac_f16_e32 v1, 0x291e, v0
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; GFX10-GISEL-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v2
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; GFX10-GISEL-NEXT: v_cmp_gt_f16_e64 s4, 0, v1
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; GFX10-GISEL-NEXT: s_or_b32 s4, vcc_lo, s4
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; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
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; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-SDAG-LABEL: test_D139469_f16:
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; GFX11-SDAG: ; %bb.0: ; %bb
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; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-SDAG-NEXT: v_mov_b32_e32 v1, 0x211e
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; GFX11-SDAG-NEXT: v_mul_f16_e32 v2, 0x291e, v0
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; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-SDAG-NEXT: v_fmac_f16_e32 v1, 0x291e, v0
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; GFX11-SDAG-NEXT: v_min_f16_e32 v0, v2, v1
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; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1)
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; GFX11-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
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; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
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; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX11-GISEL-LABEL: test_D139469_f16:
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; GFX11-GISEL: ; %bb.0: ; %bb
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; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0x211e
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; GFX11-GISEL-NEXT: v_mul_f16_e32 v2, 0x291e, v0
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; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
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; GFX11-GISEL-NEXT: v_fmac_f16_e32 v1, 0x291e, v0
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; GFX11-GISEL-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v2
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; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_1)
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; GFX11-GISEL-NEXT: v_cmp_gt_f16_e64 s0, 0, v1
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; GFX11-GISEL-NEXT: s_or_b32 s0, vcc_lo, s0
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; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
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; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
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; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
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bb:
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%i = fmul contract half %arg, 0xH291E
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%i1 = fcmp olt half %i, 0xH0000
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%i2 = fadd contract half %i, 0xH211E
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%i3 = fcmp olt half %i2, 0xH0000
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%i4 = or i1 %i1, %i3
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%i5 = zext i1 %i4 to i32
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ret i32 %i5
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}
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define <2 x i32> @test_D139469_v2f16(<2 x half> %arg) {
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; GFX9-SDAG-LABEL: test_D139469_v2f16:
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; GFX9-SDAG: ; %bb.0: ; %bb
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; GFX9-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-SDAG-NEXT: s_movk_i32 s4, 0x291e
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; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0x211e
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; GFX9-SDAG-NEXT: v_pk_mul_f16 v1, v0, s4 op_sel_hi:[1,0]
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; GFX9-SDAG-NEXT: v_pk_fma_f16 v0, v0, s4, v2 op_sel_hi:[1,0,0]
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; GFX9-SDAG-NEXT: v_pk_min_f16 v1, v1, v0
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; GFX9-SDAG-NEXT: v_mov_b32_e32 v2, 0
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; GFX9-SDAG-NEXT: v_cmp_gt_f16_e32 vcc, 0, v1
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; GFX9-SDAG-NEXT: v_cmp_lt_f16_sdwa s[4:5], v1, v2 src0_sel:WORD_1 src1_sel:DWORD
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; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc
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; GFX9-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
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; GFX9-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX9-GISEL-LABEL: test_D139469_v2f16:
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; GFX9-GISEL: ; %bb.0: ; %bb
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; GFX9-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v1, 0x291e291e
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; GFX9-GISEL-NEXT: v_pk_mul_f16 v2, v0, v1
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v3, 0
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; GFX9-GISEL-NEXT: v_cmp_gt_f16_e32 vcc, 0, v2
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; GFX9-GISEL-NEXT: v_cmp_lt_f16_sdwa s[6:7], v2, v3 src0_sel:WORD_1 src1_sel:DWORD
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; GFX9-GISEL-NEXT: v_mov_b32_e32 v2, 0x211e211e
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; GFX9-GISEL-NEXT: v_pk_fma_f16 v0, v0, v1, v2
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; GFX9-GISEL-NEXT: v_cmp_gt_f16_e64 s[4:5], 0, v0
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; GFX9-GISEL-NEXT: v_cmp_lt_f16_sdwa s[8:9], v0, v3 src0_sel:WORD_1 src1_sel:DWORD
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; GFX9-GISEL-NEXT: s_or_b64 s[4:5], vcc, s[4:5]
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; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s[4:5]
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; GFX9-GISEL-NEXT: s_or_b64 s[4:5], s[6:7], s[8:9]
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; GFX9-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s[4:5]
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; GFX9-GISEL-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-SDAG-LABEL: test_D139469_v2f16:
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; GFX10-SDAG: ; %bb.0: ; %bb
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; GFX10-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-SDAG-NEXT: s_movk_i32 s4, 0x211e
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; GFX10-SDAG-NEXT: v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1]
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; GFX10-SDAG-NEXT: v_pk_fma_f16 v0, 0x291e, v0, s4 op_sel_hi:[0,1,0]
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; GFX10-SDAG-NEXT: v_mov_b32_e32 v2, 0
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; GFX10-SDAG-NEXT: v_pk_min_f16 v1, v1, v0
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; GFX10-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
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; GFX10-SDAG-NEXT: v_cmp_lt_f16_sdwa s4, v1, v2 src0_sel:WORD_1 src1_sel:DWORD
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; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
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; GFX10-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
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; GFX10-SDAG-NEXT: s_setpc_b64 s[30:31]
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;
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; GFX10-GISEL-LABEL: test_D139469_v2f16:
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; GFX10-GISEL: ; %bb.0: ; %bb
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; GFX10-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
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; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0x211e211e
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; GFX10-GISEL-NEXT: v_pk_mul_f16 v2, 0x291e291e, v0
|
|
; GFX10-GISEL-NEXT: v_pk_fma_f16 v0, 0x291e291e, v0, v1
|
|
; GFX10-GISEL-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-GISEL-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v2
|
|
; GFX10-GISEL-NEXT: v_cmp_gt_f16_e64 s4, 0, v0
|
|
; GFX10-GISEL-NEXT: v_cmp_lt_f16_sdwa s5, v2, v1 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX10-GISEL-NEXT: v_cmp_lt_f16_sdwa s6, v0, v1 src0_sel:WORD_1 src1_sel:DWORD
|
|
; GFX10-GISEL-NEXT: s_or_b32 s4, vcc_lo, s4
|
|
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s4
|
|
; GFX10-GISEL-NEXT: s_or_b32 s4, s5, s6
|
|
; GFX10-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s4
|
|
; GFX10-GISEL-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-SDAG-LABEL: test_D139469_v2f16:
|
|
; GFX11-SDAG: ; %bb.0: ; %bb
|
|
; GFX11-SDAG-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-SDAG-NEXT: s_movk_i32 s0, 0x211e
|
|
; GFX11-SDAG-NEXT: v_pk_mul_f16 v1, 0x291e, v0 op_sel_hi:[0,1]
|
|
; GFX11-SDAG-NEXT: v_pk_fma_f16 v0, 0x291e, v0, s0 op_sel_hi:[0,1,0]
|
|
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(NEXT) | instid1(VALU_DEP_1)
|
|
; GFX11-SDAG-NEXT: v_pk_min_f16 v0, v1, v0
|
|
; GFX11-SDAG-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; GFX11-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v0
|
|
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v0, 0, 1, vcc_lo
|
|
; GFX11-SDAG-NEXT: s_delay_alu instid0(VALU_DEP_3)
|
|
; GFX11-SDAG-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v1
|
|
; GFX11-SDAG-NEXT: v_cndmask_b32_e64 v1, 0, 1, vcc_lo
|
|
; GFX11-SDAG-NEXT: s_setpc_b64 s[30:31]
|
|
;
|
|
; GFX11-GISEL-LABEL: test_D139469_v2f16:
|
|
; GFX11-GISEL: ; %bb.0: ; %bb
|
|
; GFX11-GISEL-NEXT: s_waitcnt vmcnt(0) expcnt(0) lgkmcnt(0)
|
|
; GFX11-GISEL-NEXT: v_mov_b32_e32 v1, 0x211e211e
|
|
; GFX11-GISEL-NEXT: v_pk_mul_f16 v2, 0x291e291e, v0
|
|
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-GISEL-NEXT: v_pk_fma_f16 v0, 0x291e291e, v0, v1
|
|
; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v1, 16, v2
|
|
; GFX11-GISEL-NEXT: v_cmp_gt_f16_e32 vcc_lo, 0, v2
|
|
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(SKIP_1) | instid1(VALU_DEP_4)
|
|
; GFX11-GISEL-NEXT: v_lshrrev_b32_e32 v3, 16, v0
|
|
; GFX11-GISEL-NEXT: v_cmp_gt_f16_e64 s0, 0, v0
|
|
; GFX11-GISEL-NEXT: v_cmp_gt_f16_e64 s1, 0, v1
|
|
; GFX11-GISEL-NEXT: s_delay_alu instid0(VALU_DEP_3) | instskip(NEXT) | instid1(VALU_DEP_3)
|
|
; GFX11-GISEL-NEXT: v_cmp_gt_f16_e64 s2, 0, v3
|
|
; GFX11-GISEL-NEXT: s_or_b32 s0, vcc_lo, s0
|
|
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v0, 0, 1, s0
|
|
; GFX11-GISEL-NEXT: s_or_b32 s0, s1, s2
|
|
; GFX11-GISEL-NEXT: s_delay_alu instid0(SALU_CYCLE_1)
|
|
; GFX11-GISEL-NEXT: v_cndmask_b32_e64 v1, 0, 1, s0
|
|
; GFX11-GISEL-NEXT: s_setpc_b64 s[30:31]
|
|
bb:
|
|
%i = fmul contract <2 x half> %arg, <half 0xH291E, half 0xH291E>
|
|
%i1 = fcmp olt <2 x half> %i, <half 0xH0000, half 0xH0000>
|
|
%i2 = fadd contract <2 x half> %i, <half 0xH211E, half 0xH211E>
|
|
%i3 = fcmp olt <2 x half> %i2, <half 0xH0000, half 0xH0000>
|
|
%i4 = or <2 x i1> %i1, %i3
|
|
%i5 = zext <2 x i1> %i4 to <2 x i32>
|
|
ret <2 x i32> %i5
|
|
}
|