49b492048a
Consistently treat packed 16-bit operands as 32-bit values, because that's really what they are. The attempt to treat them differently was ultimately incorrect and lead to miscompiles, e.g. when using non-splat constants such as (1, 0) as operands. Recognize 32-bit float constants for i/u16 instructions. This is a bit odd conceptually, but it matches HW behavior and SP3. Remove isFoldableLiteralV216; there was too much magic in the dependency between it and its use in SIFoldOperands. Instead, we now simply rely on checking whether a constant is an inline constant, and trying a bunch of permutations of the low and high halves. This is more obviously correct and leads to some new cases where inline constants are used as shown by tests. Move the logic for switching packed add vs. sub into SIFoldOperands. This has two benefits: all logic that optimizes for inline constants in packed math is now in one place; and it applies to both SelectionDAG and GISel paths. Disable the use of opsel with v_dot* instructions on gfx11. They are documented to ignore opsel on src0 and src1. It may be interesting to re-enable to use of opsel on src2 as a future optimization. A similar "proper" fix of what inline constants mean could potentially be applied to unpacked 16-bit ops. However, it's less clear what the benefit would be, and there are surely places where we'd have to carefully audit whether values are properly sign- or zero-extended. It is best to keep such a change separate. Fixes: Corruption in FSR 2.0 (latent bug exposed by an LLPC change)
1038 lines
42 KiB
LLVM
1038 lines
42 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -march=amdgcn -mcpu=gfx900 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GCN,GFX9
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; RUN: llc -march=amdgcn -mcpu=tonga -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GCN,VI
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; RUN: llc -march=amdgcn -mcpu=gfx1010 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GFX10
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; RUN: llc -march=amdgcn -mcpu=gfx1100 -mattr=-flat-for-global -verify-machineinstrs < %s | FileCheck %s -enable-var-scope -check-prefixes=GFX11
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; FIXME: Need to handle non-uniform case for function below (load without gep).
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define amdgpu_kernel void @v_test_sub_v2i16(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {
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; GFX9-LABEL: v_test_sub_v2i16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: global_load_dword v2, v0, s[2:3] glc
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; GFX9-NEXT: s_waitcnt vmcnt(0)
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; GFX9-NEXT: s_mov_b32 s7, 0xf000
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; GFX9-NEXT: s_mov_b32 s6, -1
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; GFX9-NEXT: v_pk_sub_i16 v0, v1, v2
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; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX9-NEXT: s_endpgm
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;
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; VI-LABEL: v_test_sub_v2i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: v_mov_b32_e32 v1, s7
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; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
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; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
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; VI-NEXT: v_mov_b32_e32 v3, s1
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; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
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; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
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; VI-NEXT: flat_load_dword v0, v[0:1] glc
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: flat_load_dword v1, v[2:3] glc
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; VI-NEXT: s_waitcnt vmcnt(0)
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; VI-NEXT: s_mov_b32 s7, 0xf000
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; VI-NEXT: s_mov_b32 s6, -1
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; VI-NEXT: v_sub_u16_e32 v2, v0, v1
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; VI-NEXT: v_sub_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
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; VI-NEXT: v_or_b32_e32 v0, v2, v0
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; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; VI-NEXT: s_endpgm
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;
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; GFX10-LABEL: v_test_sub_v2i16:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
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; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: global_load_dword v1, v0, s[6:7] glc dlc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: global_load_dword v2, v0, s[2:3] glc dlc
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; GFX10-NEXT: s_waitcnt vmcnt(0)
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; GFX10-NEXT: s_waitcnt_depctr 0xffe3
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; GFX10-NEXT: s_mov_b32 s7, 0x31016000
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; GFX10-NEXT: s_mov_b32 s6, -1
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; GFX10-NEXT: v_pk_sub_i16 v0, v1, v2
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; GFX10-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: v_test_sub_v2i16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
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; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: global_load_b32 v1, v0, s[6:7] glc dlc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] glc dlc
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; GFX11-NEXT: s_waitcnt vmcnt(0)
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; GFX11-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-NEXT: s_mov_b32 s6, -1
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; GFX11-NEXT: v_pk_sub_i16 v0, v1, v0
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; GFX11-NEXT: buffer_store_b32 v0, off, s[4:7], 0
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%gep.out = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i32 %tid
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%gep.in0 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in0, i32 %tid
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%gep.in1 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in1, i32 %tid
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%a = load volatile <2 x i16>, ptr addrspace(1) %gep.in0
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%b = load volatile <2 x i16>, ptr addrspace(1) %gep.in1
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%add = sub <2 x i16> %a, %b
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store <2 x i16> %add, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_test_sub_v2i16(ptr addrspace(1) %out, ptr addrspace(4) %in0, ptr addrspace(4) %in1) #1 {
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; GFX9-LABEL: s_test_sub_v2i16:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx2 s[8:9], s[0:1], 0x34
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; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; GFX9-NEXT: s_mov_b32 s3, 0xf000
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; GFX9-NEXT: s_mov_b32 s2, -1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: s_load_dword s10, s[8:9], 0x0
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; GFX9-NEXT: s_load_dword s11, s[6:7], 0x0
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; GFX9-NEXT: s_mov_b32 s0, s4
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; GFX9-NEXT: s_mov_b32 s1, s5
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s10
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; GFX9-NEXT: v_pk_sub_i16 v0, s11, v0
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; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX9-NEXT: s_endpgm
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;
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; VI-LABEL: s_test_sub_v2i16:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
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; VI-NEXT: s_mov_b32 s3, 0xf000
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; VI-NEXT: s_mov_b32 s2, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_load_dword s6, s[6:7], 0x0
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; VI-NEXT: s_load_dword s7, s[0:1], 0x0
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; VI-NEXT: s_mov_b32 s0, s4
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; VI-NEXT: s_mov_b32 s1, s5
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_lshr_b32 s4, s6, 16
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; VI-NEXT: s_lshr_b32 s5, s7, 16
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; VI-NEXT: s_sub_i32 s6, s6, s7
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; VI-NEXT: s_sub_i32 s4, s4, s5
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; VI-NEXT: s_and_b32 s5, s6, 0xffff
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; VI-NEXT: s_lshl_b32 s4, s4, 16
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; VI-NEXT: s_or_b32 s4, s5, s4
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; VI-NEXT: v_mov_b32_e32 v0, s4
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; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; VI-NEXT: s_endpgm
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;
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; GFX10-LABEL: s_test_sub_v2i16:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_clause 0x1
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; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
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; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: s_load_dword s0, s[6:7], 0x0
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; GFX10-NEXT: s_load_dword s1, s[2:3], 0x0
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; GFX10-NEXT: s_mov_b32 s7, 0x31016000
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; GFX10-NEXT: s_mov_b32 s6, -1
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_pk_sub_i16 v0, s0, s1
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; GFX10-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: s_test_sub_v2i16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_clause 0x1
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; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: s_load_b32 s2, s[6:7], 0x0
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; GFX11-NEXT: s_load_b32 s0, s[0:1], 0x0
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; GFX11-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-NEXT: s_mov_b32 s6, -1
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_pk_sub_i16 v0, s2, s0
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; GFX11-NEXT: buffer_store_b32 v0, off, s[4:7], 0
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%a = load <2 x i16>, ptr addrspace(4) %in0
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%b = load <2 x i16>, ptr addrspace(4) %in1
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%add = sub <2 x i16> %a, %b
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store <2 x i16> %add, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @s_test_sub_self_v2i16(ptr addrspace(1) %out, ptr addrspace(4) %in0) #1 {
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; GCN-LABEL: s_test_sub_self_v2i16:
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; GCN: ; %bb.0:
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; GCN-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GCN-NEXT: s_mov_b32 s3, 0xf000
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; GCN-NEXT: s_mov_b32 s2, -1
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; GCN-NEXT: v_mov_b32_e32 v0, 0
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; GCN-NEXT: s_waitcnt lgkmcnt(0)
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; GCN-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GCN-NEXT: s_endpgm
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;
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; GFX10-LABEL: s_test_sub_self_v2i16:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x24
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; GFX10-NEXT: v_mov_b32_e32 v0, 0
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; GFX10-NEXT: s_mov_b32 s3, 0x31016000
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; GFX10-NEXT: s_mov_b32 s2, -1
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], 0
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: s_test_sub_self_v2i16:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x24
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; GFX11-NEXT: v_mov_b32_e32 v0, 0
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; GFX11-NEXT: s_mov_b32 s3, 0x31016000
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; GFX11-NEXT: s_mov_b32 s2, -1
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%a = load <2 x i16>, ptr addrspace(4) %in0
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%add = sub <2 x i16> %a, %a
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store <2 x i16> %add, ptr addrspace(1) %out
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ret void
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}
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; FIXME: VI should not scalarize arg access.
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define amdgpu_kernel void @s_test_sub_v2i16_kernarg(ptr addrspace(1) %out, <2 x i16> %a, <2 x i16> %b) #1 {
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; GFX9-LABEL: s_test_sub_v2i16_kernarg:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX9-NEXT: s_mov_b32 s7, 0xf000
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; GFX9-NEXT: s_mov_b32 s6, -1
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: v_mov_b32_e32 v0, s3
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; GFX9-NEXT: s_mov_b32 s4, s0
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; GFX9-NEXT: s_mov_b32 s5, s1
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; GFX9-NEXT: v_pk_sub_i16 v0, s2, v0
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; GFX9-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX9-NEXT: s_endpgm
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;
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; VI-LABEL: s_test_sub_v2i16_kernarg:
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; VI: ; %bb.0:
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; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; VI-NEXT: s_mov_b32 s7, 0xf000
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; VI-NEXT: s_mov_b32 s6, -1
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; VI-NEXT: s_waitcnt lgkmcnt(0)
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; VI-NEXT: s_mov_b32 s4, s0
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; VI-NEXT: s_mov_b32 s5, s1
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; VI-NEXT: s_lshr_b32 s0, s2, 16
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; VI-NEXT: s_lshr_b32 s1, s3, 16
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; VI-NEXT: s_sub_i32 s0, s0, s1
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; VI-NEXT: s_sub_i32 s1, s2, s3
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; VI-NEXT: s_lshl_b32 s0, s0, 16
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; VI-NEXT: s_and_b32 s1, s1, 0xffff
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; VI-NEXT: s_or_b32 s0, s1, s0
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; VI-NEXT: v_mov_b32_e32 v0, s0
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; VI-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; VI-NEXT: s_endpgm
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;
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; GFX10-LABEL: s_test_sub_v2i16_kernarg:
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; GFX10: ; %bb.0:
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; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX10-NEXT: s_mov_b32 s7, 0x31016000
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; GFX10-NEXT: s_mov_b32 s6, -1
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; GFX10-NEXT: s_waitcnt lgkmcnt(0)
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; GFX10-NEXT: v_pk_sub_i16 v0, s2, s3
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; GFX10-NEXT: s_mov_b32 s4, s0
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; GFX10-NEXT: s_mov_b32 s5, s1
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; GFX10-NEXT: buffer_store_dword v0, off, s[4:7], 0
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; GFX10-NEXT: s_endpgm
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;
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; GFX11-LABEL: s_test_sub_v2i16_kernarg:
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; GFX11: ; %bb.0:
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; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
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; GFX11-NEXT: s_mov_b32 s7, 0x31016000
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; GFX11-NEXT: s_mov_b32 s6, -1
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; GFX11-NEXT: s_waitcnt lgkmcnt(0)
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; GFX11-NEXT: v_pk_sub_i16 v0, s2, s3
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; GFX11-NEXT: s_mov_b32 s4, s0
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; GFX11-NEXT: s_mov_b32 s5, s1
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; GFX11-NEXT: buffer_store_b32 v0, off, s[4:7], 0
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; GFX11-NEXT: s_nop 0
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; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
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; GFX11-NEXT: s_endpgm
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%add = sub <2 x i16> %a, %b
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store <2 x i16> %add, ptr addrspace(1) %out
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ret void
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}
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define amdgpu_kernel void @v_test_sub_v2i16_constant(ptr addrspace(1) %out, ptr addrspace(1) %in0) #1 {
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; GFX9-LABEL: v_test_sub_v2i16_constant:
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; GFX9: ; %bb.0:
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; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
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; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
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; GFX9-NEXT: s_mov_b32 s4, 0x1c8007b
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; GFX9-NEXT: s_waitcnt lgkmcnt(0)
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; GFX9-NEXT: global_load_dword v0, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_test_sub_v2i16_constant:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, s3
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: flat_load_dword v0, v[0:1] glc
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0xfffffe38
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
; VI-NEXT: v_add_u16_e32 v2, 0xff85, v0
|
|
; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: v_test_sub_v2i16_constant:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] glc dlc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
|
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
|
|
; GFX10-NEXT: s_mov_b32 s2, -1
|
|
; GFX10-NEXT: v_pk_sub_i16 v0, v0, 0x1c8007b
|
|
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_test_sub_v2i16_constant:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] glc dlc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
|
|
; GFX11-NEXT: s_mov_b32 s2, -1
|
|
; GFX11-NEXT: v_pk_sub_i16 v0, v0, 0x1c8007b
|
|
; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.out = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i32 %tid
|
|
%gep.in0 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in0, i32 %tid
|
|
%a = load volatile <2 x i16>, ptr addrspace(1) %gep.in0
|
|
%add = sub <2 x i16> %a, <i16 123, i16 456>
|
|
store <2 x i16> %add, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
|
define amdgpu_kernel void @v_test_sub_v2i16_neg_constant(ptr addrspace(1) %out, ptr addrspace(1) %in0) #1 {
|
|
; GFX9-LABEL: v_test_sub_v2i16_neg_constant:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_mov_b32 s4, 0xfc21fcb3
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v0, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
; GFX9-NEXT: v_pk_sub_i16 v0, v0, s4
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_test_sub_v2i16_neg_constant:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, s3
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: flat_load_dword v0, v[0:1] glc
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0x3df
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
; VI-NEXT: v_add_u16_e32 v2, 0x34d, v0
|
|
; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: v_test_sub_v2i16_neg_constant:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] glc dlc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
|
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
|
|
; GFX10-NEXT: s_mov_b32 s2, -1
|
|
; GFX10-NEXT: v_pk_sub_i16 v0, v0, 0xfc21fcb3
|
|
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_test_sub_v2i16_neg_constant:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] glc dlc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
|
|
; GFX11-NEXT: s_mov_b32 s2, -1
|
|
; GFX11-NEXT: v_pk_sub_i16 v0, v0, 0xfc21fcb3
|
|
; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.out = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i32 %tid
|
|
%gep.in0 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in0, i32 %tid
|
|
%a = load volatile <2 x i16>, ptr addrspace(1) %gep.in0
|
|
%add = sub <2 x i16> %a, <i16 -845, i16 -991>
|
|
store <2 x i16> %add, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_test_sub_v2i16_inline_neg1(ptr addrspace(1) %out, ptr addrspace(1) %in0) #1 {
|
|
; GFX9-LABEL: v_test_sub_v2i16_inline_neg1:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v0, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
; GFX9-NEXT: v_pk_sub_i16 v0, v0, -1
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_test_sub_v2i16_inline_neg1:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, s3
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: flat_load_dword v0, v[0:1] glc
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, 1
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
; VI-NEXT: v_add_u16_e32 v2, 1, v0
|
|
; VI-NEXT: v_add_u16_sdwa v0, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_e32 v0, v2, v0
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: v_test_sub_v2i16_inline_neg1:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] glc dlc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
|
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
|
|
; GFX10-NEXT: s_mov_b32 s2, -1
|
|
; GFX10-NEXT: v_pk_sub_i16 v0, v0, -1
|
|
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_test_sub_v2i16_inline_neg1:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] glc dlc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
|
|
; GFX11-NEXT: s_mov_b32 s2, -1
|
|
; GFX11-NEXT: v_pk_sub_i16 v0, v0, -1
|
|
; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.out = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i32 %tid
|
|
%gep.in0 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in0, i32 %tid
|
|
%a = load volatile <2 x i16>, ptr addrspace(1) %gep.in0
|
|
%add = sub <2 x i16> %a, <i16 -1, i16 -1>
|
|
store <2 x i16> %add, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
define amdgpu_kernel void @v_test_sub_v2i16_inline_lo_zero_hi(ptr addrspace(1) %out, ptr addrspace(1) %in0) #1 {
|
|
; GFX9-LABEL: v_test_sub_v2i16_inline_lo_zero_hi:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v0, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
; GFX9-NEXT: v_pk_sub_i16 v0, v0, 32
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_test_sub_v2i16_inline_lo_zero_hi:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, s3
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: flat_load_dword v0, v[0:1] glc
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
; VI-NEXT: v_and_b32_e32 v1, 0xffff0000, v0
|
|
; VI-NEXT: v_subrev_u16_e32 v0, 32, v0
|
|
; VI-NEXT: v_or_b32_e32 v0, v0, v1
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: v_test_sub_v2i16_inline_lo_zero_hi:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] glc dlc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
|
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
|
|
; GFX10-NEXT: s_mov_b32 s2, -1
|
|
; GFX10-NEXT: v_pk_sub_i16 v0, v0, 32
|
|
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_test_sub_v2i16_inline_lo_zero_hi:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] glc dlc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
|
|
; GFX11-NEXT: s_mov_b32 s2, -1
|
|
; GFX11-NEXT: v_pk_sub_i16 v0, v0, 32
|
|
; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.out = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i32 %tid
|
|
%gep.in0 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in0, i32 %tid
|
|
%a = load volatile <2 x i16>, ptr addrspace(1) %gep.in0
|
|
%add = sub <2 x i16> %a, <i16 32, i16 0>
|
|
store <2 x i16> %add, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; The high element gives fp
|
|
define amdgpu_kernel void @v_test_sub_v2i16_inline_fp_split(ptr addrspace(1) %out, ptr addrspace(1) %in0) #1 {
|
|
; GFX9-LABEL: v_test_sub_v2i16_inline_fp_split:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v0, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_mov_b32 s3, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s2, -1
|
|
; GFX9-NEXT: v_pk_sub_i16 v0, v0, 1.0
|
|
; GFX9-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_test_sub_v2i16_inline_fp_split:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; VI-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, s3
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s2, v0
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: flat_load_dword v0, v[0:1] glc
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0xffffc080
|
|
; VI-NEXT: s_mov_b32 s3, 0xf000
|
|
; VI-NEXT: s_mov_b32 s2, -1
|
|
; VI-NEXT: v_add_u16_sdwa v1, v0, v1 dst_sel:WORD_1 dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:DWORD
|
|
; VI-NEXT: v_or_b32_sdwa v0, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_0 src1_sel:DWORD
|
|
; VI-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: v_test_sub_v2i16_inline_fp_split:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_load_dwordx4 s[0:3], s[0:1], 0x24
|
|
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_load_dword v0, v0, s[2:3] glc dlc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
|
; GFX10-NEXT: s_mov_b32 s3, 0x31016000
|
|
; GFX10-NEXT: s_mov_b32 s2, -1
|
|
; GFX10-NEXT: v_pk_sub_i16 v0, v0, 1.0
|
|
; GFX10-NEXT: buffer_store_dword v0, off, s[0:3], 0
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_test_sub_v2i16_inline_fp_split:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_load_b128 s[0:3], s[0:1], 0x24
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v0, v0, s[2:3] glc dlc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s3, 0x31016000
|
|
; GFX11-NEXT: s_mov_b32 s2, -1
|
|
; GFX11-NEXT: v_pk_sub_i16 v0, v0, 1.0
|
|
; GFX11-NEXT: buffer_store_b32 v0, off, s[0:3], 0
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.out = getelementptr inbounds <2 x i16>, ptr addrspace(1) %out, i32 %tid
|
|
%gep.in0 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in0, i32 %tid
|
|
%a = load volatile <2 x i16>, ptr addrspace(1) %gep.in0
|
|
%add = sub <2 x i16> %a, <i16 0, i16 16256>
|
|
store <2 x i16> %add, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
|
define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {
|
|
; GFX9-LABEL: v_test_sub_v2i16_zext_to_v2i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v2, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s6, -1
|
|
; GFX9-NEXT: v_pk_sub_i16 v0, v1, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_test_sub_v2i16_zext_to_v2i32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; VI-NEXT: flat_load_dword v1, v[0:1] glc
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: flat_load_dword v2, v[2:3] glc
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_mov_b32 s7, 0xf000
|
|
; VI-NEXT: s_mov_b32 s6, -1
|
|
; VI-NEXT: v_sub_u16_e32 v0, v1, v2
|
|
; VI-NEXT: v_sub_u16_sdwa v1, v1, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: v_test_sub_v2i16_zext_to_v2i32:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_clause 0x1
|
|
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
|
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_load_dword v1, v0, s[6:7] glc dlc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: global_load_dword v2, v0, s[2:3] glc dlc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
|
; GFX10-NEXT: s_mov_b32 s7, 0x31016000
|
|
; GFX10-NEXT: s_mov_b32 s6, -1
|
|
; GFX10-NEXT: v_pk_sub_i16 v0, v1, v2
|
|
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX10-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_test_sub_v2i16_zext_to_v2i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_clause 0x1
|
|
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[6:7] glc dlc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] glc dlc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s7, 0x31016000
|
|
; GFX11-NEXT: s_mov_b32 s6, -1
|
|
; GFX11-NEXT: v_pk_sub_i16 v0, v1, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; GFX11-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[4:7], 0
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.out = getelementptr inbounds <2 x i32>, ptr addrspace(1) %out, i32 %tid
|
|
%gep.in0 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in0, i32 %tid
|
|
%gep.in1 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in1, i32 %tid
|
|
%a = load volatile <2 x i16>, ptr addrspace(1) %gep.in0
|
|
%b = load volatile <2 x i16>, ptr addrspace(1) %gep.in1
|
|
%add = sub <2 x i16> %a, %b
|
|
%ext = zext <2 x i16> %add to <2 x i32>
|
|
store <2 x i32> %ext, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
|
define amdgpu_kernel void @v_test_sub_v2i16_zext_to_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {
|
|
; GFX9-LABEL: v_test_sub_v2i16_zext_to_v2i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v2, v0, s[6:7] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v3, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s6, -1
|
|
; GFX9-NEXT: v_pk_sub_i16 v0, v2, v3
|
|
; GFX9-NEXT: v_alignbit_b32 v2, 0, v0, 16
|
|
; GFX9-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX9-NEXT: v_mov_b32_e32 v3, v1
|
|
; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_test_sub_v2i16_zext_to_v2i64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; VI-NEXT: flat_load_dword v4, v[0:1] glc
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: flat_load_dword v2, v[2:3] glc
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, 0
|
|
; VI-NEXT: s_mov_b32 s7, 0xf000
|
|
; VI-NEXT: s_mov_b32 s6, -1
|
|
; VI-NEXT: v_mov_b32_e32 v3, v1
|
|
; VI-NEXT: v_sub_u16_e32 v0, v4, v2
|
|
; VI-NEXT: v_sub_u16_sdwa v2, v4, v2 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: v_test_sub_v2i16_zext_to_v2i64:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_clause 0x1
|
|
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
|
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_load_dword v1, v0, s[6:7] glc dlc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: global_load_dword v2, v0, s[2:3] glc dlc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
|
; GFX10-NEXT: s_mov_b32 s7, 0x31016000
|
|
; GFX10-NEXT: s_mov_b32 s6, -1
|
|
; GFX10-NEXT: v_pk_sub_i16 v0, v1, v2
|
|
; GFX10-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX10-NEXT: v_alignbit_b32 v2, 0, v0, 16
|
|
; GFX10-NEXT: v_and_b32_e32 v0, 0xffff, v0
|
|
; GFX10-NEXT: v_mov_b32_e32 v3, v1
|
|
; GFX10-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_test_sub_v2i16_zext_to_v2i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_clause 0x1
|
|
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[6:7] glc dlc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] glc dlc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s7, 0x31016000
|
|
; GFX11-NEXT: s_mov_b32 s6, -1
|
|
; GFX11-NEXT: v_pk_sub_i16 v0, v1, v0
|
|
; GFX11-NEXT: v_mov_b32_e32 v1, 0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-NEXT: v_alignbit_b32 v2, 0, v0, 16
|
|
; GFX11-NEXT: v_dual_mov_b32 v3, v1 :: v_dual_and_b32 v0, 0xffff, v0
|
|
; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[4:7], 0
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.out = getelementptr inbounds <2 x i64>, ptr addrspace(1) %out, i32 %tid
|
|
%gep.in0 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in0, i32 %tid
|
|
%gep.in1 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in1, i32 %tid
|
|
%a = load volatile <2 x i16>, ptr addrspace(1) %gep.in0
|
|
%b = load volatile <2 x i16>, ptr addrspace(1) %gep.in1
|
|
%add = sub <2 x i16> %a, %b
|
|
%ext = zext <2 x i16> %add to <2 x i64>
|
|
store <2 x i64> %ext, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
|
define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i32(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {
|
|
; GFX9-LABEL: v_test_sub_v2i16_sext_to_v2i32:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v2, v0, s[2:3] glc
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s6, -1
|
|
; GFX9-NEXT: v_pk_sub_i16 v0, v1, v2
|
|
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 16, v0
|
|
; GFX9-NEXT: v_bfe_i32 v0, v0, 0, 16
|
|
; GFX9-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_test_sub_v2i16_sext_to_v2i32:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; VI-NEXT: flat_load_dword v0, v[0:1] glc
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: flat_load_dword v1, v[2:3] glc
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: s_mov_b32 s7, 0xf000
|
|
; VI-NEXT: s_mov_b32 s6, -1
|
|
; VI-NEXT: v_sub_u16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; VI-NEXT: v_sub_u16_e32 v0, v0, v1
|
|
; VI-NEXT: v_bfe_i32 v0, v0, 0, 16
|
|
; VI-NEXT: v_bfe_i32 v1, v2, 0, 16
|
|
; VI-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: v_test_sub_v2i16_sext_to_v2i32:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_clause 0x1
|
|
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
|
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: global_load_dword v1, v0, s[6:7] glc dlc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: global_load_dword v2, v0, s[2:3] glc dlc
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
|
; GFX10-NEXT: s_mov_b32 s7, 0x31016000
|
|
; GFX10-NEXT: s_mov_b32 s6, -1
|
|
; GFX10-NEXT: v_pk_sub_i16 v0, v1, v2
|
|
; GFX10-NEXT: v_ashrrev_i32_e32 v1, 16, v0
|
|
; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 16
|
|
; GFX10-NEXT: buffer_store_dwordx2 v[0:1], off, s[4:7], 0
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_test_sub_v2i16_sext_to_v2i32:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_clause 0x1
|
|
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[6:7] glc dlc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: global_load_b32 v0, v0, s[0:1] glc dlc
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: s_mov_b32 s7, 0x31016000
|
|
; GFX11-NEXT: s_mov_b32 s6, -1
|
|
; GFX11-NEXT: v_pk_sub_i16 v0, v1, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1)
|
|
; GFX11-NEXT: v_ashrrev_i32_e32 v1, 16, v0
|
|
; GFX11-NEXT: v_bfe_i32 v0, v0, 0, 16
|
|
; GFX11-NEXT: buffer_store_b64 v[0:1], off, s[4:7], 0
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.out = getelementptr inbounds <2 x i32>, ptr addrspace(1) %out, i32 %tid
|
|
%gep.in0 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in0, i32 %tid
|
|
%gep.in1 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in1, i32 %tid
|
|
%a = load volatile <2 x i16>, ptr addrspace(1) %gep.in0
|
|
%b = load volatile <2 x i16>, ptr addrspace(1) %gep.in1
|
|
%add = sub <2 x i16> %a, %b
|
|
%ext = sext <2 x i16> %add to <2 x i32>
|
|
store <2 x i32> %ext, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
; FIXME: Need to handle non-uniform case for function below (load without gep).
|
|
define amdgpu_kernel void @v_test_sub_v2i16_sext_to_v2i64(ptr addrspace(1) %out, ptr addrspace(1) %in0, ptr addrspace(1) %in1) #1 {
|
|
; GFX9-LABEL: v_test_sub_v2i16_sext_to_v2i64:
|
|
; GFX9: ; %bb.0:
|
|
; GFX9-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; GFX9-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
|
; GFX9-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX9-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX9-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX9-NEXT: global_load_dword v2, v0, s[2:3]
|
|
; GFX9-NEXT: s_mov_b32 s7, 0xf000
|
|
; GFX9-NEXT: s_mov_b32 s6, -1
|
|
; GFX9-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX9-NEXT: v_pk_sub_i16 v1, v1, v2
|
|
; GFX9-NEXT: v_lshrrev_b32_e32 v2, 16, v1
|
|
; GFX9-NEXT: v_bfe_i32 v0, v1, 0, 16
|
|
; GFX9-NEXT: v_bfe_i32 v2, v2, 0, 16
|
|
; GFX9-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX9-NEXT: v_ashrrev_i32_e32 v3, 31, v2
|
|
; GFX9-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
|
; GFX9-NEXT: s_endpgm
|
|
;
|
|
; VI-LABEL: v_test_sub_v2i16_sext_to_v2i64:
|
|
; VI: ; %bb.0:
|
|
; VI-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; VI-NEXT: s_load_dwordx2 s[0:1], s[0:1], 0x34
|
|
; VI-NEXT: v_lshlrev_b32_e32 v2, 2, v0
|
|
; VI-NEXT: s_waitcnt lgkmcnt(0)
|
|
; VI-NEXT: v_mov_b32_e32 v1, s7
|
|
; VI-NEXT: v_add_u32_e32 v0, vcc, s6, v2
|
|
; VI-NEXT: v_addc_u32_e32 v1, vcc, 0, v1, vcc
|
|
; VI-NEXT: v_mov_b32_e32 v3, s1
|
|
; VI-NEXT: v_add_u32_e32 v2, vcc, s0, v2
|
|
; VI-NEXT: v_addc_u32_e32 v3, vcc, 0, v3, vcc
|
|
; VI-NEXT: flat_load_dword v0, v[0:1]
|
|
; VI-NEXT: flat_load_dword v1, v[2:3]
|
|
; VI-NEXT: s_mov_b32 s7, 0xf000
|
|
; VI-NEXT: s_mov_b32 s6, -1
|
|
; VI-NEXT: s_waitcnt vmcnt(0)
|
|
; VI-NEXT: v_sub_u16_sdwa v2, v0, v1 dst_sel:DWORD dst_unused:UNUSED_PAD src0_sel:WORD_1 src1_sel:WORD_1
|
|
; VI-NEXT: v_sub_u16_e32 v0, v0, v1
|
|
; VI-NEXT: v_bfe_i32 v0, v0, 0, 16
|
|
; VI-NEXT: v_bfe_i32 v2, v2, 0, 16
|
|
; VI-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; VI-NEXT: v_ashrrev_i32_e32 v3, 31, v2
|
|
; VI-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
|
; VI-NEXT: s_endpgm
|
|
;
|
|
; GFX10-LABEL: v_test_sub_v2i16_sext_to_v2i64:
|
|
; GFX10: ; %bb.0:
|
|
; GFX10-NEXT: s_clause 0x1
|
|
; GFX10-NEXT: s_load_dwordx4 s[4:7], s[0:1], 0x24
|
|
; GFX10-NEXT: s_load_dwordx2 s[2:3], s[0:1], 0x34
|
|
; GFX10-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX10-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX10-NEXT: s_clause 0x1
|
|
; GFX10-NEXT: global_load_dword v1, v0, s[6:7]
|
|
; GFX10-NEXT: global_load_dword v2, v0, s[2:3]
|
|
; GFX10-NEXT: s_waitcnt_depctr 0xffe3
|
|
; GFX10-NEXT: s_mov_b32 s7, 0x31016000
|
|
; GFX10-NEXT: s_mov_b32 s6, -1
|
|
; GFX10-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX10-NEXT: v_pk_sub_i16 v0, v1, v2
|
|
; GFX10-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; GFX10-NEXT: v_bfe_i32 v0, v0, 0, 16
|
|
; GFX10-NEXT: v_bfe_i32 v2, v1, 0, 16
|
|
; GFX10-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX10-NEXT: v_ashrrev_i32_e32 v3, 31, v2
|
|
; GFX10-NEXT: buffer_store_dwordx4 v[0:3], off, s[4:7], 0
|
|
; GFX10-NEXT: s_endpgm
|
|
;
|
|
; GFX11-LABEL: v_test_sub_v2i16_sext_to_v2i64:
|
|
; GFX11: ; %bb.0:
|
|
; GFX11-NEXT: s_clause 0x1
|
|
; GFX11-NEXT: s_load_b128 s[4:7], s[0:1], 0x24
|
|
; GFX11-NEXT: s_load_b64 s[0:1], s[0:1], 0x34
|
|
; GFX11-NEXT: v_lshlrev_b32_e32 v0, 2, v0
|
|
; GFX11-NEXT: s_waitcnt lgkmcnt(0)
|
|
; GFX11-NEXT: s_clause 0x1
|
|
; GFX11-NEXT: global_load_b32 v1, v0, s[6:7]
|
|
; GFX11-NEXT: global_load_b32 v0, v0, s[0:1]
|
|
; GFX11-NEXT: s_mov_b32 s7, 0x31016000
|
|
; GFX11-NEXT: s_mov_b32 s6, -1
|
|
; GFX11-NEXT: s_waitcnt vmcnt(0)
|
|
; GFX11-NEXT: v_pk_sub_i16 v0, v1, v0
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_1) | instskip(SKIP_1) | instid1(VALU_DEP_2)
|
|
; GFX11-NEXT: v_lshrrev_b32_e32 v1, 16, v0
|
|
; GFX11-NEXT: v_bfe_i32 v0, v0, 0, 16
|
|
; GFX11-NEXT: v_bfe_i32 v2, v1, 0, 16
|
|
; GFX11-NEXT: s_delay_alu instid0(VALU_DEP_2) | instskip(NEXT) | instid1(VALU_DEP_2)
|
|
; GFX11-NEXT: v_ashrrev_i32_e32 v1, 31, v0
|
|
; GFX11-NEXT: v_ashrrev_i32_e32 v3, 31, v2
|
|
; GFX11-NEXT: buffer_store_b128 v[0:3], off, s[4:7], 0
|
|
; GFX11-NEXT: s_nop 0
|
|
; GFX11-NEXT: s_sendmsg sendmsg(MSG_DEALLOC_VGPRS)
|
|
; GFX11-NEXT: s_endpgm
|
|
%tid = call i32 @llvm.amdgcn.workitem.id.x()
|
|
%gep.out = getelementptr inbounds <2 x i64>, ptr addrspace(1) %out, i32 %tid
|
|
%gep.in0 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in0, i32 %tid
|
|
%gep.in1 = getelementptr inbounds <2 x i16>, ptr addrspace(1) %in1, i32 %tid
|
|
%a = load <2 x i16>, ptr addrspace(1) %gep.in0
|
|
%b = load <2 x i16>, ptr addrspace(1) %gep.in1
|
|
%add = sub <2 x i16> %a, %b
|
|
%ext = sext <2 x i16> %add to <2 x i64>
|
|
store <2 x i64> %ext, ptr addrspace(1) %out
|
|
ret void
|
|
}
|
|
|
|
declare i32 @llvm.amdgcn.workitem.id.x() #0
|
|
|
|
attributes #0 = { nounwind readnone }
|
|
attributes #1 = { nounwind }
|