llvm-project

History

Roman Tereshin 5e51fac39a [MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)

MIParser wasn't able to parse LLTs like `<4 x p0>`, fixing that.

Reviewers: qcolombet t.p.northover aditya_nandakumar

Reviewed By: qcolombet

Subscribers: rovka, kristof.beyls, llvm-commits

Differential Revision: https://reviews.llvm.org/D46490

llvm-svn: 331712

2018-05-08 02:02:50 +00:00

AArch64

[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)

2018-05-08 02:02:50 +00:00

AMDGPU

[MIR-Canon] Fixing a test failure caused by COPY Folding.

2018-04-16 09:31:49 +00:00

ARM

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Generic

[MIR] Add support for MachineFrameInfo::LocalFrameSize

2018-04-06 08:56:25 +00:00

Hexagon

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

Mips

Followup on Proposal to move MIR physical register namespace to '$' sigil.

2018-01-31 22:04:26 +00:00

NVPTX

[MIR] Repurposing '$' sigil used by external symbols. Replacing with '&'.

2018-01-10 00:56:48 +00:00

PowerPC

[if-converter] Handle BBs that terminate in ret during diamond conversion

2018-04-19 17:26:46 +00:00

WebAssembly

[MIRParser][GlobalISel] Parsing vector pointer types (<M x pA>)

2018-05-08 02:02:50 +00:00

X86

MachineInst support mapping SDNode fast math flags for support in Back End code generation

2018-05-03 00:07:56 +00:00

README

Add README describing the intention of test/CodeGen/MIR

2016-12-09 20:16:12 +00:00

README

This directory contains tests for the MIR file format parser and printer. It
was necessary to split the tests across different targets as no single target
covers all features available in machine IR.

Tests for codegen passes should NOT be here but in test/CodeGen/sometarget. As
a rule of thumb this directory should only contain tests using
'llc -run-pass none'.