shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen
History
Min-Yih Hsu cdcaef876c
[RISCV][GISel] Add ISel support for SHXADD_UW and SLLI.UW (#69972) 
This patch also includes:
  - Remove legacy non_imm12 PatLeaf from RISCVInstrInfoZb.td
- Implement a custom GlobalISel operand renderer for TrailingZeros
SDNodeXForm
2023-10-24 16:26:38 -07:00
..
AArch64
[AArch64][GlobalISel] Add support for post-indexed loads/stores. (#69532)
2023-10-24 13:51:59 -07:00
AMDGPU
[AMDGPU] Fix subreg check in the SIFixSGPRCopies (#70007)
2023-10-24 01:44:58 -07:00
ARC
…
ARM
[ARM] Lower i1 concat via MVETRUNC
2023-10-18 19:40:11 +01:00
AVR
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
BPF
[MemDep] Use EarliestEscapeInfo (#69727)
2023-10-23 09:57:26 +02:00
CSKY
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
DirectX
[SPIRV][DX] Share one test between backends (#65975)
2023-09-21 12:15:55 +02:00
Generic
[AsmPrint] Correctly factor function entry count when dumping MBB frequencies (#67826)
2023-09-29 18:06:53 -07:00
Hexagon
Update call-long1.ll
2023-10-23 11:55:42 -05:00
Inputs
…
Lanai
[test] Change llc -march= to -mtriple= & llvm-mc -arch= to -triple=
2023-09-11 15:11:01 -07:00
LoongArch
[LoongArch] Improve codegen for atomic cmpxchg ops (#69339)
2023-10-19 09:21:51 +08:00
M68k
[M68k] Add new calling convention M68k_RTD
2023-10-15 16:12:31 -07:00
Mips
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
MIR
[YAMLParser] Improve plain scalar spec compliance (#68946)
2023-10-17 11:28:14 -06:00
MLRegAlloc
Revert "[mlgo] Fix tests post 760e7d0"
2023-10-24 08:43:32 -07:00
MSP430
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
NVPTX
[NVPTX] Add a test to verify the .version with sm_90(a)
2023-10-24 18:01:48 +02:00
PowerPC
ISel: introduce vector ISD::LRINT, ISD::LLRINT; custom RISCV lowering (#66924)
2023-10-19 13:05:04 +01:00
RISCV
[RISCV][GISel] Add ISel support for SHXADD_UW and SLLI.UW (#69972)
2023-10-24 16:26:38 -07:00
SPARC
[Sparc] Remove duplicate ALU and SETHI instructions (NFCI) (#66851)
2023-10-10 20:34:20 +03:00
SPIRV
[SPIR-V] Emit proper pointer type for OpenCL kernel arguments (#67726)
2023-10-18 20:51:53 -07:00
SystemZ
Typos: 'maxium', 'minium'
2023-10-23 10:42:28 +02:00
Thumb
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
Thumb2
[ARM] Lower i1 concat via MVETRUNC
2023-10-18 19:40:11 +01:00
VE
Revert "[CodeGen] Really renumber slot indexes before register allocation (#67038)"
2023-10-09 12:31:32 +01:00
WebAssembly
[wasm] Don't crash on non-simple value types during shuffle combine
2023-10-24 12:35:43 +02:00
WinCFGuard
…
WinEH
…
X86
[X86] Add scalar isel test coverage for AND/OR/XOR types
2023-10-24 15:13:17 +01:00
XCore
[test] Change llc -march= to -mtriple=
2023-09-11 14:42:37 -07:00