llvm-project/llvm/test/CodeGen/X86/GlobalISel/select-mul-scalar.mir
pvanhout c3cfbbc416 [GlobalISel] Add dead flags to implicit defs in ISel
Checks for implicit defs that are unused within a pattern and mark them as dead.

This is done directly at the TableGen level forr efficiency.
The instructions are directly created with the "dead" operand and no further analysis is needed later.

Reviewed By: arsenm

Differential Revision: https://reviews.llvm.org/D157273
2023-08-09 14:20:51 +02:00

105 lines
2.8 KiB
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# NOTE: Assertions have been autogenerated by utils/update_mir_test_checks.py
# RUN: llc -mtriple=x86_64-linux-gnu -run-pass=instruction-select -verify-machineinstrs %s -o - | FileCheck %s --check-prefix=ALL
--- |
define i16 @test_mul_i16(i16 %arg1, i16 %arg2) {
%ret = mul i16 %arg1, %arg2
ret i16 %ret
}
define i32 @test_mul_i32(i32 %arg1, i32 %arg2) {
%ret = mul i32 %arg1, %arg2
ret i32 %ret
}
define i64 @test_mul_i64(i64 %arg1, i64 %arg2) {
%ret = mul i64 %arg1, %arg2
ret i64 %ret
}
...
---
name: test_mul_i16
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; ALL-LABEL: name: test_mul_i16
; ALL: liveins: $edi, $esi
; ALL-NEXT: {{ $}}
; ALL-NEXT: [[COPY:%[0-9]+]]:gr16 = COPY $di
; ALL-NEXT: [[COPY1:%[0-9]+]]:gr16 = COPY $si
; ALL-NEXT: [[IMUL16rr:%[0-9]+]]:gr16 = IMUL16rr [[COPY]], [[COPY1]], implicit-def dead $eflags
; ALL-NEXT: $ax = COPY [[IMUL16rr]]
; ALL-NEXT: RET 0, implicit $ax
%0(s16) = COPY $di
%1(s16) = COPY $si
%2(s16) = G_MUL %0, %1
$ax = COPY %2(s16)
RET 0, implicit $ax
...
---
name: test_mul_i32
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.1 (%ir-block.0):
liveins: $edi, $esi
; ALL-LABEL: name: test_mul_i32
; ALL: liveins: $edi, $esi
; ALL-NEXT: {{ $}}
; ALL-NEXT: [[COPY:%[0-9]+]]:gr32 = COPY $edi
; ALL-NEXT: [[COPY1:%[0-9]+]]:gr32 = COPY $esi
; ALL-NEXT: [[IMUL32rr:%[0-9]+]]:gr32 = IMUL32rr [[COPY]], [[COPY1]], implicit-def dead $eflags
; ALL-NEXT: $eax = COPY [[IMUL32rr]]
; ALL-NEXT: RET 0, implicit $eax
%0(s32) = COPY $edi
%1(s32) = COPY $esi
%2(s32) = G_MUL %0, %1
$eax = COPY %2(s32)
RET 0, implicit $eax
...
---
name: test_mul_i64
alignment: 16
legalized: true
regBankSelected: true
registers:
- { id: 0, class: gpr }
- { id: 1, class: gpr }
- { id: 2, class: gpr }
body: |
bb.1 (%ir-block.0):
liveins: $rdi, $rsi
; ALL-LABEL: name: test_mul_i64
; ALL: liveins: $rdi, $rsi
; ALL-NEXT: {{ $}}
; ALL-NEXT: [[COPY:%[0-9]+]]:gr64 = COPY $rdi
; ALL-NEXT: [[COPY1:%[0-9]+]]:gr64 = COPY $rsi
; ALL-NEXT: [[IMUL64rr:%[0-9]+]]:gr64 = IMUL64rr [[COPY]], [[COPY1]], implicit-def dead $eflags
; ALL-NEXT: $rax = COPY [[IMUL64rr]]
; ALL-NEXT: RET 0, implicit $rax
%0(s64) = COPY $rdi
%1(s64) = COPY $rsi
%2(s64) = G_MUL %0, %1
$rax = COPY %2(s64)
RET 0, implicit $rax
...