81fae0d5e3
Summary: The documentation at https://llvm.org/docs/AMDGPUUsage.html#memory-scopes states that these 'one-as' modifiers are more specific versions of the scopes that only apply to a specific address space. This doesn't make sense for fences which have no associated address space to use, and it's a more restrictive version the normal scope. This should not tbe the default behavior, but it is currently emitted in all cases except for sequentially consistent.
260 lines
11 KiB
C
260 lines
11 KiB
C
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py UTC_ARGS: --version 5
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// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding \
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// RUN: -fvisibility=hidden | FileCheck --check-prefix=AMDGCN %s
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// RUN: %clang_cc1 %s -emit-llvm -o - -triple=amdgcn-amd-amdhsa -ffreestanding \
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// RUN: -cl-std=CL2.0 -fvisibility=hidden | FileCheck --check-prefix=AMDGCN %s
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// RUN: %clang_cc1 %s -emit-llvm -o - -triple=spirv64-unknown-unknown -ffreestanding \
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// RUN: -fvisibility=hidden | FileCheck --check-prefix=SPIRV %s
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// RUN: %clang_cc1 %s -emit-llvm -o - -triple=x86_64-unknown-linux-gnu -ffreestanding \
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// RUN: -fvisibility=hidden | FileCheck --check-prefix=X86_64 %s
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// AMDGCN-LABEL: define hidden void @fe1a(
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// AMDGCN-SAME: ) #[[ATTR0:[0-9]+]] {
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// AMDGCN-NEXT: [[ENTRY:.*:]]
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// AMDGCN-NEXT: fence syncscope("workgroup") release
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// AMDGCN-NEXT: ret void
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//
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// SPIRV-LABEL: define hidden spir_func void @fe1a(
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// SPIRV-SAME: ) #[[ATTR0:[0-9]+]] {
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// SPIRV-NEXT: [[ENTRY:.*:]]
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// SPIRV-NEXT: fence syncscope("workgroup") release
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// SPIRV-NEXT: ret void
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//
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// X86_64-LABEL: define hidden void @fe1a(
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// X86_64-SAME: ) #[[ATTR0:[0-9]+]] {
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// X86_64-NEXT: [[ENTRY:.*:]]
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// X86_64-NEXT: fence release
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// X86_64-NEXT: ret void
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//
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void fe1a() {
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__scoped_atomic_thread_fence(__ATOMIC_RELEASE, __MEMORY_SCOPE_WRKGRP);
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}
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// AMDGCN-LABEL: define hidden void @fe1b(
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// AMDGCN-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {
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// AMDGCN-NEXT: [[ENTRY:.*:]]
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// AMDGCN-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
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// AMDGCN-NEXT: [[ORD_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[ORD_ADDR]] to ptr
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// AMDGCN-NEXT: store i32 [[ORD]], ptr [[ORD_ADDR_ASCAST]], align 4
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// AMDGCN-NEXT: [[TMP0:%.*]] = load i32, ptr [[ORD_ADDR_ASCAST]], align 4
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// AMDGCN-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
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// AMDGCN-NEXT: i32 1, label %[[ACQUIRE:.*]]
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// AMDGCN-NEXT: i32 2, label %[[ACQUIRE]]
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// AMDGCN-NEXT: i32 3, label %[[RELEASE:.*]]
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// AMDGCN-NEXT: i32 4, label %[[ACQREL:.*]]
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// AMDGCN-NEXT: i32 5, label %[[SEQCST:.*]]
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// AMDGCN-NEXT: ]
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// AMDGCN: [[ATOMIC_SCOPE_CONTINUE]]:
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// AMDGCN-NEXT: ret void
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// AMDGCN: [[ACQUIRE]]:
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// AMDGCN-NEXT: fence syncscope("workgroup") acquire
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// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// AMDGCN: [[RELEASE]]:
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// AMDGCN-NEXT: fence syncscope("workgroup") release
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// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// AMDGCN: [[ACQREL]]:
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// AMDGCN-NEXT: fence syncscope("workgroup") acq_rel
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// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// AMDGCN: [[SEQCST]]:
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// AMDGCN-NEXT: fence syncscope("workgroup") seq_cst
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// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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//
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// SPIRV-LABEL: define hidden spir_func void @fe1b(
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// SPIRV-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {
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// SPIRV-NEXT: [[ENTRY:.*:]]
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// SPIRV-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 4
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// SPIRV-NEXT: store i32 [[ORD]], ptr [[ORD_ADDR]], align 4
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// SPIRV-NEXT: [[TMP0:%.*]] = load i32, ptr [[ORD_ADDR]], align 4
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// SPIRV-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
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// SPIRV-NEXT: i32 1, label %[[ACQUIRE:.*]]
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// SPIRV-NEXT: i32 2, label %[[ACQUIRE]]
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// SPIRV-NEXT: i32 3, label %[[RELEASE:.*]]
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// SPIRV-NEXT: i32 4, label %[[ACQREL:.*]]
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// SPIRV-NEXT: i32 5, label %[[SEQCST:.*]]
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// SPIRV-NEXT: ]
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// SPIRV: [[ATOMIC_SCOPE_CONTINUE]]:
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// SPIRV-NEXT: ret void
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// SPIRV: [[ACQUIRE]]:
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// SPIRV-NEXT: fence syncscope("workgroup") acquire
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// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// SPIRV: [[RELEASE]]:
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// SPIRV-NEXT: fence syncscope("workgroup") release
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// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// SPIRV: [[ACQREL]]:
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// SPIRV-NEXT: fence syncscope("workgroup") acq_rel
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// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// SPIRV: [[SEQCST]]:
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// SPIRV-NEXT: fence syncscope("workgroup") seq_cst
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// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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//
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// X86_64-LABEL: define hidden void @fe1b(
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// X86_64-SAME: i32 noundef [[ORD:%.*]]) #[[ATTR0]] {
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// X86_64-NEXT: [[ENTRY:.*:]]
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// X86_64-NEXT: [[ORD_ADDR:%.*]] = alloca i32, align 4
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// X86_64-NEXT: store i32 [[ORD]], ptr [[ORD_ADDR]], align 4
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// X86_64-NEXT: [[TMP0:%.*]] = load i32, ptr [[ORD_ADDR]], align 4
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// X86_64-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
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// X86_64-NEXT: i32 1, label %[[ACQUIRE:.*]]
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// X86_64-NEXT: i32 2, label %[[ACQUIRE]]
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// X86_64-NEXT: i32 3, label %[[RELEASE:.*]]
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// X86_64-NEXT: i32 4, label %[[ACQREL:.*]]
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// X86_64-NEXT: i32 5, label %[[SEQCST:.*]]
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// X86_64-NEXT: ]
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// X86_64: [[ATOMIC_SCOPE_CONTINUE]]:
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// X86_64-NEXT: ret void
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// X86_64: [[ACQUIRE]]:
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// X86_64-NEXT: fence acquire
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// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// X86_64: [[RELEASE]]:
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// X86_64-NEXT: fence release
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// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// X86_64: [[ACQREL]]:
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// X86_64-NEXT: fence acq_rel
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// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// X86_64: [[SEQCST]]:
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// X86_64-NEXT: fence seq_cst
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// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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//
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void fe1b(int ord) {
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__scoped_atomic_thread_fence(ord, __MEMORY_SCOPE_WRKGRP);
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}
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// AMDGCN-LABEL: define hidden void @fe1c(
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// AMDGCN-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {
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// AMDGCN-NEXT: [[ENTRY:.*:]]
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// AMDGCN-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4, addrspace(5)
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// AMDGCN-NEXT: [[SCOPE_ADDR_ASCAST:%.*]] = addrspacecast ptr addrspace(5) [[SCOPE_ADDR]] to ptr
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// AMDGCN-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR_ASCAST]], align 4
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// AMDGCN-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR_ASCAST]], align 4
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// AMDGCN-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
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// AMDGCN-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]
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// AMDGCN-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]
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// AMDGCN-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]
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// AMDGCN-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]
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// AMDGCN-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]
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// AMDGCN-NEXT: ]
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// AMDGCN: [[ATOMIC_SCOPE_CONTINUE]]:
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// AMDGCN-NEXT: ret void
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// AMDGCN: [[DEVICE_SCOPE]]:
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// AMDGCN-NEXT: fence syncscope("agent") release
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// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// AMDGCN: [[SYSTEM_SCOPE]]:
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// AMDGCN-NEXT: fence release
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// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// AMDGCN: [[WORKGROUP_SCOPE]]:
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// AMDGCN-NEXT: fence syncscope("workgroup") release
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// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// AMDGCN: [[WAVEFRONT_SCOPE]]:
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// AMDGCN-NEXT: fence syncscope("wavefront") release
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// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// AMDGCN: [[SINGLE_SCOPE]]:
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// AMDGCN-NEXT: fence syncscope("singlethread") release
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// AMDGCN-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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//
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// SPIRV-LABEL: define hidden spir_func void @fe1c(
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// SPIRV-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {
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// SPIRV-NEXT: [[ENTRY:.*:]]
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// SPIRV-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4
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// SPIRV-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR]], align 4
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// SPIRV-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR]], align 4
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// SPIRV-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
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// SPIRV-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]
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// SPIRV-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]
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// SPIRV-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]
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// SPIRV-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]
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// SPIRV-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]
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// SPIRV-NEXT: ]
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// SPIRV: [[ATOMIC_SCOPE_CONTINUE]]:
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// SPIRV-NEXT: ret void
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// SPIRV: [[DEVICE_SCOPE]]:
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// SPIRV-NEXT: fence syncscope("device") release
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// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// SPIRV: [[SYSTEM_SCOPE]]:
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// SPIRV-NEXT: fence release
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// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// SPIRV: [[WORKGROUP_SCOPE]]:
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// SPIRV-NEXT: fence syncscope("workgroup") release
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// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// SPIRV: [[WAVEFRONT_SCOPE]]:
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// SPIRV-NEXT: fence syncscope("subgroup") release
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// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// SPIRV: [[SINGLE_SCOPE]]:
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// SPIRV-NEXT: fence syncscope("singlethread") release
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// SPIRV-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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//
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// X86_64-LABEL: define hidden void @fe1c(
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// X86_64-SAME: i32 noundef [[SCOPE:%.*]]) #[[ATTR0]] {
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// X86_64-NEXT: [[ENTRY:.*:]]
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// X86_64-NEXT: [[SCOPE_ADDR:%.*]] = alloca i32, align 4
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// X86_64-NEXT: store i32 [[SCOPE]], ptr [[SCOPE_ADDR]], align 4
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// X86_64-NEXT: [[TMP0:%.*]] = load i32, ptr [[SCOPE_ADDR]], align 4
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// X86_64-NEXT: switch i32 [[TMP0]], label %[[ATOMIC_SCOPE_CONTINUE:.*]] [
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// X86_64-NEXT: i32 1, label %[[DEVICE_SCOPE:.*]]
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// X86_64-NEXT: i32 0, label %[[SYSTEM_SCOPE:.*]]
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// X86_64-NEXT: i32 2, label %[[WORKGROUP_SCOPE:.*]]
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// X86_64-NEXT: i32 3, label %[[WAVEFRONT_SCOPE:.*]]
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// X86_64-NEXT: i32 4, label %[[SINGLE_SCOPE:.*]]
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// X86_64-NEXT: ]
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// X86_64: [[ATOMIC_SCOPE_CONTINUE]]:
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// X86_64-NEXT: ret void
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// X86_64: [[DEVICE_SCOPE]]:
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// X86_64-NEXT: fence release
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// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// X86_64: [[SYSTEM_SCOPE]]:
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// X86_64-NEXT: fence release
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// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// X86_64: [[WORKGROUP_SCOPE]]:
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// X86_64-NEXT: fence release
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// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// X86_64: [[WAVEFRONT_SCOPE]]:
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// X86_64-NEXT: fence release
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// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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// X86_64: [[SINGLE_SCOPE]]:
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// X86_64-NEXT: fence release
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// X86_64-NEXT: br label %[[ATOMIC_SCOPE_CONTINUE]]
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//
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void fe1c(int scope) {
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__scoped_atomic_thread_fence(__ATOMIC_RELEASE, scope);
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}
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// AMDGCN-LABEL: define hidden void @fe2a(
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// AMDGCN-SAME: ) #[[ATTR0]] {
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// AMDGCN-NEXT: [[ENTRY:.*:]]
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// AMDGCN-NEXT: ret void
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//
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// SPIRV-LABEL: define hidden spir_func void @fe2a(
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// SPIRV-SAME: ) #[[ATTR0]] {
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// SPIRV-NEXT: [[ENTRY:.*:]]
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// SPIRV-NEXT: ret void
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//
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// X86_64-LABEL: define hidden void @fe2a(
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// X86_64-SAME: ) #[[ATTR0]] {
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// X86_64-NEXT: [[ENTRY:.*:]]
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// X86_64-NEXT: ret void
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//
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void fe2a() {
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__scoped_atomic_thread_fence(999, __MEMORY_SCOPE_SYSTEM);
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}
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// AMDGCN-LABEL: define hidden void @fe2b(
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// AMDGCN-SAME: ) #[[ATTR0]] {
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// AMDGCN-NEXT: [[ENTRY:.*:]]
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// AMDGCN-NEXT: fence release
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// AMDGCN-NEXT: ret void
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//
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// SPIRV-LABEL: define hidden spir_func void @fe2b(
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// SPIRV-SAME: ) #[[ATTR0]] {
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// SPIRV-NEXT: [[ENTRY:.*:]]
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// SPIRV-NEXT: fence release
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// SPIRV-NEXT: ret void
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//
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// X86_64-LABEL: define hidden void @fe2b(
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// X86_64-SAME: ) #[[ATTR0]] {
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// X86_64-NEXT: [[ENTRY:.*:]]
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// X86_64-NEXT: fence release
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// X86_64-NEXT: ret void
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//
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void fe2b() {
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__scoped_atomic_thread_fence(__ATOMIC_RELEASE, 999);
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}
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