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llvm-project/llvm/test/Transforms/LoopVectorize/RISCV
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Mel Chen 2f5500e4cf
[LV] Improve the test coverage for strided access. nfc (#155981) 
Add tests for strided access with UF > 1, and introduce a new test case
@constant_stride_reinterpret.
2025-09-03 10:19:36 +00:00
..
bf16.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
blend-any-of-reduction-cost.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
blocks-with-dead-instructions.ll
[VPlan] Reassociate (x & y) & z -> x & (y & z) (#155383)
2025-09-03 01:09:19 +00:00
dead-ops-cost.ll
[LV][EVL] Support interleaved access with tail folding by EVL (#152070)
2025-09-01 21:20:06 +08:00
defaults.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
divrem.ll
[VPlan] Fold common edges away in convertPhisToBlends (#150368)
2025-09-01 07:03:33 +00:00
evl-compatible-loops.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
evl-iv-simplify.ll
[LV][EVL] Introduce the EVLIndVarSimplify Pass for EVL-vectorized loops (#131005)
2025-05-14 13:49:50 -07:00
f16.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
first-order-recurrence-scalable-vf1.ll
[VPlan] Add dedicated user for resume phi with epilogue vectorization.
2025-08-10 21:21:16 +01:00
fminimumnum.ll
[VPlan] Add VPlan-based addMinIterCheck, replace ILV for non-epilogue. (#153643)
2025-08-26 15:52:31 +01:00
force-vect-msg.ll
[LV][RISCV] Try fixing Windows buildbot failure in force-vect-msg.ll. NFC
2025-08-09 21:09:36 +08:00
gather-scatter-cost.ll
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386)
2025-09-02 11:43:27 +08:00
illegal-type.ll
[VPlan] Don't access canonical IV in VPWidenPointerInduction::execute.
2025-03-15 21:32:48 +00:00
induction-costs.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
inloop-reduction.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
interleaved-accesses-zve32x.ll
…
interleaved-accesses.ll
[LV][EVL] Support interleaved access with tail folding by EVL (#152070)
2025-09-01 21:20:06 +08:00
interleaved-cost.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
interleaved-masked-access.ll
[LV][EVL] Support interleaved access with tail folding by EVL (#152070)
2025-09-01 21:20:06 +08:00
interleaved-store-with-gap.ll
[LV] Fix gap mask requirement for interleaved access (#151105)
2025-08-01 14:24:30 +08:00
lit.local.cfg
…
lmul.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
low-trip-count.ll
Reapply "[VPlan] Remove trivial dead VPPhi cycles."
2025-08-12 22:09:30 +01:00
mask-index-type.ll
[VPlan] Fold common edges away in convertPhisToBlends (#150368)
2025-09-01 07:03:33 +00:00
masked_gather_scatter.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
only-compute-cost-for-vplan-vfs.ll
[VPlan] Support VPWidenPointerInductionRecipes with EVL tail folding (#152110)
2025-08-07 10:54:24 +08:00
ordered-reduction.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
partial-reduce-dot-product.ll
[LV] Use shl for ((VF * Step) * vscale) in createStepForVF. (#153495)
2025-08-14 19:27:51 +01:00
pr87378-vpinstruction-or-drop-poison-generating-flags.ll
[VPlan] Reassociate (x & y) & z -> x & (y & z) (#155383)
2025-09-03 01:09:19 +00:00
pr88802.ll
[VPlan] Fold common edges away in convertPhisToBlends (#150368)
2025-09-01 07:03:33 +00:00
pr154103.ll
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386)
2025-09-02 11:43:27 +08:00
preserve-dbg-loc.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
reductions.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
reg-usage-bf16.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
reg-usage-f16.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
reg-usage-maxbandwidth.ll
[LV][VPlan] Reduce register usage of VPEVLBasedIVPHIRecipe. (#154482)
2025-08-21 07:39:01 +08:00
reg-usage.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
remark-reductions.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
riscv-interleaved.ll
[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)
2025-07-14 21:59:35 +08:00
riscv-unroll.ll
[VPlan] Remove VPVectorPointer for part 0 after unrolling. (#149735)
2025-07-27 13:53:26 +01:00
riscv-vector-reverse.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
safe-dep-distance.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
scalable-basics.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
scalable-tailfold.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
scalable-vf-hint.ll
…
select-cmp-reduction.ll
[VPlan] Fold common edges away in convertPhisToBlends (#150368)
2025-09-01 07:03:33 +00:00
select-invariant-cond-cost.ll
…
short-trip-count.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
strided-accesses.ll
[LV] Improve the test coverage for strided access. nfc (#155981)
2025-09-03 10:19:36 +00:00
tail-folding-bin-unary-ops-args.ll
[VPlan] Add VPlan-based addMinIterCheck, replace ILV for non-epilogue. (#153643)
2025-08-26 15:52:31 +01:00
tail-folding-call-intrinsics.ll
[VPlan] Add VPlan-based addMinIterCheck, replace ILV for non-epilogue. (#153643)
2025-08-26 15:52:31 +01:00
tail-folding-cast-intrinsics.ll
[VPlan] Add VPlan-based addMinIterCheck, replace ILV for non-epilogue. (#153643)
2025-08-26 15:52:31 +01:00
tail-folding-cond-reduction.ll
[VPlan] Fold common edges away in convertPhisToBlends (#150368)
2025-09-01 07:03:33 +00:00
tail-folding-cost.ll
[RISCV][LV] Remove redundant -force-tail-folding-style from tests. NFC
2025-07-28 16:11:01 +08:00
tail-folding-div.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
tail-folding-fixed-order-recurrence.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
tail-folding-gather-scatter.ll
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386)
2025-09-02 11:43:27 +08:00
tail-folding-inloop-reduction.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
tail-folding-interleave.ll
[Reland] "[RISCV][TTI] Implement getAddressComputationCost() in RISCV TTI. #149955" (#156386)
2025-09-02 11:43:27 +08:00
tail-folding-intermediate-store.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
tail-folding-iv32.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
tail-folding-known-no-overflow.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
tail-folding-masked-loadstore.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
tail-folding-no-masking.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
tail-folding-ordered-reduction.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
tail-folding-reduction-cost.ll
[RISCV][LV] Use predicate-else-scalar-epilogue flag in tail folding tests. NFC
2025-07-28 17:04:00 +08:00
tail-folding-reduction.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
tail-folding-reverse-load-store.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
tail-folding-safe-dep-distance.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
tail-folding-uniform-store.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
truncate-to-minimal-bitwidth-cost.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
truncate-to-minimal-bitwidth-evl-crash.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
type-info-cache-evl-crash.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
uniform-load-store.ll
[VPlan] Fold common edges away in convertPhisToBlends (#150368)
2025-09-01 07:03:33 +00:00
unroll-in-loop-vectorizer.ll
[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)
2025-07-14 21:59:35 +08:00
veclib-function-calls.ll
…
vector-loop-backedge-elimination-with-evl.ll
Reapply "[VPlan] Remove trivial dead VPPhi cycles."
2025-08-12 22:09:30 +01:00
vectorize-vp-intrinsics.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
vf-will-not-generate-any-vector-insts.ll
[VPlan] Replace EVL branch condition with (branch-on-count AVLNext, 0) (#152167)
2025-08-26 11:19:19 +00:00
vplan-riscv-vector-reverse.ll
[RISCV] Enable tail folding by default (#151681)
2025-08-08 14:26:23 +08:00
vplan-vp-call-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-cast-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-intrinsics-fixed-order-recurrence.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-intrinsics-reduction.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
vplan-vp-intrinsics.ll
[VPlan] Create AVL as a phi from TC -> 0 with EVL tail folding (#151481)
2025-08-01 11:00:05 +08:00
zvl32b.ll
…