6c412b6c6f
In [1], a few new insns are proposed to expand BPF ISA to
. fixing the limitation of existing insn (e.g., 16bit jmp offset)
. adding new insns which may improve code quality
(sign_ext_ld, sign_ext_mov, st)
. feature complete (sdiv, smod)
. better user experience (bswap)
This patch implemented insn encoding for
. sign-extended load
. sign-extended mov
. sdiv/smod
. bswap insns
. unconditional jump with 32bit offset
The new bswap insns are generated under cpu=v4 for __builtin_bswap.
For cpu=v3 or earlier, for __builtin_bswap, be or le insns are generated
which is not intuitive for the user.
To support 32-bit branch offset, a 32-bit ja (JMPL) insn is implemented.
For conditional branch which is beyond 16-bit offset, llvm will do
some transformation 'cond_jmp' -> 'cond_jmp + jmpl' to simulate 32bit
conditional jmp. See BPFMIPeephole.cpp for details. The algorithm is
hueristic based. I have tested bpf selftest pyperf600 with unroll account
600 which can indeed generate 32-bit jump insn, e.g.,
13: 06 00 00 00 9b cd 00 00 gotol +0xcd9b <LBB0_6619>
Eduard is working on to add 'st' insn to cpu=v4.
A list of llc flags:
disable-ldsx, disable-movsx, disable-bswap,
disable-sdiv-smod, disable-gotol
can be used to disable a particular insn for cpu v4.
For example, user can do:
llc -march=bpf -mcpu=v4 -disable-movsx t.ll
to enable cpu v4 without movsx insns.
References:
[1] https://lore.kernel.org/bpf/4bfe98be-5333-1c7e-2f6d-42486c8ec039@meta.com/
Differential Revision: https://reviews.llvm.org/D144829
118 lines
3.5 KiB
C++
118 lines
3.5 KiB
C++
//===-- BPFInstPrinter.cpp - Convert BPF MCInst to asm syntax -------------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This class prints an BPF MCInst to a .s file.
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//
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//===----------------------------------------------------------------------===//
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#include "BPF.h"
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#include "MCTargetDesc/BPFInstPrinter.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCRegister.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/FormattedStream.h"
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using namespace llvm;
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#define DEBUG_TYPE "asm-printer"
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// Include the auto-generated portion of the assembly writer.
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#include "BPFGenAsmWriter.inc"
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void BPFInstPrinter::printInst(const MCInst *MI, uint64_t Address,
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StringRef Annot, const MCSubtargetInfo &STI,
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raw_ostream &O) {
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printInstruction(MI, Address, O);
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printAnnotation(O, Annot);
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}
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static void printExpr(const MCExpr *Expr, raw_ostream &O) {
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#ifndef NDEBUG
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const MCSymbolRefExpr *SRE;
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if (const MCBinaryExpr *BE = dyn_cast<MCBinaryExpr>(Expr))
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SRE = dyn_cast<MCSymbolRefExpr>(BE->getLHS());
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else
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SRE = dyn_cast<MCSymbolRefExpr>(Expr);
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assert(SRE && "Unexpected MCExpr type.");
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MCSymbolRefExpr::VariantKind Kind = SRE->getKind();
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assert(Kind == MCSymbolRefExpr::VK_None);
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#endif
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O << *Expr;
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}
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void BPFInstPrinter::printOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O, const char *Modifier) {
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assert((Modifier == nullptr || Modifier[0] == 0) && "No modifiers supported");
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isReg()) {
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O << getRegisterName(Op.getReg());
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} else if (Op.isImm()) {
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O << formatImm((int32_t)Op.getImm());
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} else {
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assert(Op.isExpr() && "Expected an expression");
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printExpr(Op.getExpr(), O);
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}
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}
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void BPFInstPrinter::printMemOperand(const MCInst *MI, int OpNo, raw_ostream &O,
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const char *Modifier) {
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const MCOperand &RegOp = MI->getOperand(OpNo);
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const MCOperand &OffsetOp = MI->getOperand(OpNo + 1);
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// register
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assert(RegOp.isReg() && "Register operand not a register");
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O << getRegisterName(RegOp.getReg());
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// offset
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if (OffsetOp.isImm()) {
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auto Imm = OffsetOp.getImm();
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if (Imm >= 0)
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O << " + " << formatImm(Imm);
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else
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O << " - " << formatImm(-Imm);
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} else {
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assert(0 && "Expected an immediate");
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}
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}
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void BPFInstPrinter::printImm64Operand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm())
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O << formatImm(Op.getImm());
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else if (Op.isExpr())
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printExpr(Op.getExpr(), O);
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else
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O << Op;
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}
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void BPFInstPrinter::printBrTargetOperand(const MCInst *MI, unsigned OpNo,
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raw_ostream &O) {
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const MCOperand &Op = MI->getOperand(OpNo);
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if (Op.isImm()) {
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if (MI->getOpcode() == BPF::JMPL) {
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int32_t Imm = Op.getImm();
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O << ((Imm >= 0) ? "+" : "") << formatImm(Imm);
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} else {
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int16_t Imm = Op.getImm();
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O << ((Imm >= 0) ? "+" : "") << formatImm(Imm);
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}
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} else if (Op.isExpr()) {
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printExpr(Op.getExpr(), O);
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} else {
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O << Op;
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}
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}
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