a63bd7e99b
In a recent series of refactorings (described here: https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295), I greatly increased the number of IMPLICIT_DEF operands to our vector instructions. This has turned out to have an unexpected negative impact because MachineCSE does not CSE IMPLICIT_DEFs, and thus does not CSE any instruction with an IMPLICIT_DEF operand. SelectionDAG *does* CSE the same case, but that only covers the same block case, not the cross block case. This lead to the performance regression reported in https://github.com/llvm/llvm-project/issues/64282. This change is a slightly ugly hack to side step the issue. Instead of fixing the root cause (lack of CSE for IMPLICIT_DEF) or undoing the operand changes, we leave the extra operand in place, and use NoReg in place of IMPLICIT_DEF. I then convert back to IMPLICIT_DEF just before register allocation so that ProcessImplicitDefs and TwoAddressInstructions can do the normal transforms to Undef tied registers. We may end up backporting this into the 17.x release branch. Given how late in the release cycle this is landing, that's much less likely now, but still a possibility. Differential Revision: https://reviews.llvm.org/D156909
529 lines
22 KiB
LLVM
529 lines
22 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple riscv32 -mattr=+m,+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
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; RUN: llc -mtriple riscv64 -mattr=+m,+d,+zfh,+zvfh,+v -verify-machineinstrs < %s | FileCheck %s
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define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_0(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv8i32_nxv4i32_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv2r.v v8, v12
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)
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ret <vscale x 8 x i32> %v
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}
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define <vscale x 8 x i32> @insert_nxv8i32_nxv4i32_4(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv8i32_nxv4i32_4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv2r.v v10, v12
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4)
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ret <vscale x 8 x i32> %v
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}
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define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_0(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv8i32_nxv2i32_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v8, v12
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0)
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ret <vscale x 8 x i32> %v
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}
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define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_2(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv8i32_nxv2i32_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v9, v12
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2)
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ret <vscale x 8 x i32> %v
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}
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define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_4(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv8i32_nxv2i32_4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v10, v12
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4)
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ret <vscale x 8 x i32> %v
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}
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define <vscale x 8 x i32> @insert_nxv8i32_nxv2i32_6(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv8i32_nxv2i32_6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v11, v12
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; CHECK-NEXT: ret
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%v = call <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6)
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ret <vscale x 8 x i32> %v
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}
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define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_0(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) {
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; CHECK-LABEL: insert_nxv1i8_nxv4i8_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: srli a0, a0, 3
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; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
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; CHECK-NEXT: vmv.v.v v8, v9
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0)
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ret <vscale x 4 x i8> %v
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}
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define <vscale x 4 x i8> @insert_nxv1i8_nxv4i8_3(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec) {
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; CHECK-LABEL: insert_nxv1i8_nxv4i8_3:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: srli a0, a0, 3
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; CHECK-NEXT: slli a1, a0, 1
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; CHECK-NEXT: add a1, a1, a0
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; CHECK-NEXT: add a0, a1, a0
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; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
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; CHECK-NEXT: vslideup.vx v8, v9, a1
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; CHECK-NEXT: ret
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%v = call <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
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ret <vscale x 4 x i8> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_0(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv8i32_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv4r.v v8, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 0)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv8i32_8(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv8i32_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv4r.v v12, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 8 x i32> %subvec, i64 8)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_0(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv4i32_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv2r.v v8, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 0)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_4(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv4i32_4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv2r.v v10, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 4)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_8(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv4i32_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv2r.v v12, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 8)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv4i32_12(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv4i32_12:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv2r.v v14, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 4 x i32> %subvec, i64 12)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_0(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv2i32_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v8, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 0)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_2(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv2i32_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v9, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 2)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_4(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv2i32_4:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v10, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 4)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_6(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv2i32_6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v11, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 6)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_8(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv2i32_8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v12, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 8)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_10(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv2i32_10:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v13, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 10)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_12(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv2i32_12:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v14, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 12)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv2i32_14(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv2i32_14:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vmv1r.v v15, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 2 x i32> %subvec, i64 14)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_0(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv1i32_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: srli a0, a0, 3
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; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
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; CHECK-NEXT: vmv.v.v v8, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 0)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_1(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv1i32_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: srli a0, a0, 3
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; CHECK-NEXT: add a1, a0, a0
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; CHECK-NEXT: vsetvli zero, a1, e32, m1, tu, ma
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; CHECK-NEXT: vslideup.vx v8, v16, a0
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 1)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i32> @insert_nxv16i32_nxv1i32_6(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec) {
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; CHECK-LABEL: insert_nxv16i32_nxv1i32_6:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: srli a0, a0, 3
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; CHECK-NEXT: vsetvli zero, a0, e32, m1, tu, ma
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; CHECK-NEXT: vmv.v.v v11, v16
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32> %vec, <vscale x 1 x i32> %subvec, i64 6)
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ret <vscale x 16 x i32> %v
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}
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define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_0(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
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; CHECK-LABEL: insert_nxv16i8_nxv1i8_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: srli a0, a0, 3
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; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
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; CHECK-NEXT: vmv.v.v v8, v10
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 0)
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ret <vscale x 16 x i8> %v
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}
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define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_1(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
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; CHECK-LABEL: insert_nxv16i8_nxv1i8_1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: srli a0, a0, 3
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; CHECK-NEXT: add a1, a0, a0
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; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
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; CHECK-NEXT: vslideup.vx v8, v10, a0
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 1)
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ret <vscale x 16 x i8> %v
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}
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define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_2(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
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; CHECK-LABEL: insert_nxv16i8_nxv1i8_2:
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; CHECK: # %bb.0:
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; CHECK-NEXT: csrr a0, vlenb
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; CHECK-NEXT: srli a1, a0, 3
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; CHECK-NEXT: srli a0, a0, 2
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; CHECK-NEXT: add a1, a0, a1
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; CHECK-NEXT: vsetvli zero, a1, e8, m1, tu, ma
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; CHECK-NEXT: vslideup.vx v8, v10, a0
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; CHECK-NEXT: ret
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%v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 2)
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ret <vscale x 16 x i8> %v
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}
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|
|
|
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_3(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
|
|
; CHECK-LABEL: insert_nxv16i8_nxv1i8_3:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: srli a0, a0, 3
|
|
; CHECK-NEXT: slli a1, a0, 1
|
|
; CHECK-NEXT: add a1, a1, a0
|
|
; CHECK-NEXT: add a0, a1, a0
|
|
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
|
|
; CHECK-NEXT: vslideup.vx v8, v10, a1
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 3)
|
|
ret <vscale x 16 x i8> %v
|
|
}
|
|
|
|
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_7(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
|
|
; CHECK-LABEL: insert_nxv16i8_nxv1i8_7:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: srli a1, a0, 3
|
|
; CHECK-NEXT: sub a1, a0, a1
|
|
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
|
|
; CHECK-NEXT: vslideup.vx v8, v10, a1
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 7)
|
|
ret <vscale x 16 x i8> %v
|
|
}
|
|
|
|
define <vscale x 16 x i8> @insert_nxv16i8_nxv1i8_15(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec) {
|
|
; CHECK-LABEL: insert_nxv16i8_nxv1i8_15:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: srli a1, a0, 3
|
|
; CHECK-NEXT: sub a1, a0, a1
|
|
; CHECK-NEXT: vsetvli zero, a0, e8, m1, tu, ma
|
|
; CHECK-NEXT: vslideup.vx v9, v10, a1
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8> %vec, <vscale x 1 x i8> %subvec, i64 15)
|
|
ret <vscale x 16 x i8> %v
|
|
}
|
|
|
|
define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_0(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
|
|
; CHECK-LABEL: insert_nxv32f16_nxv2f16_0:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: srli a0, a0, 2
|
|
; CHECK-NEXT: vsetvli zero, a0, e16, m1, tu, ma
|
|
; CHECK-NEXT: vmv.v.v v8, v16
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 0)
|
|
ret <vscale x 32 x half> %v
|
|
}
|
|
|
|
define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_2(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
|
|
; CHECK-LABEL: insert_nxv32f16_nxv2f16_2:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: srli a0, a0, 2
|
|
; CHECK-NEXT: add a1, a0, a0
|
|
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
|
|
; CHECK-NEXT: vslideup.vx v8, v16, a0
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 2)
|
|
ret <vscale x 32 x half> %v
|
|
}
|
|
|
|
define <vscale x 32 x half> @insert_nxv32f16_nxv2f16_26(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec) {
|
|
; CHECK-LABEL: insert_nxv32f16_nxv2f16_26:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: srli a0, a0, 2
|
|
; CHECK-NEXT: add a1, a0, a0
|
|
; CHECK-NEXT: vsetvli zero, a1, e16, m1, tu, ma
|
|
; CHECK-NEXT: vslideup.vx v14, v16, a0
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half> %vec, <vscale x 2 x half> %subvec, i64 26)
|
|
ret <vscale x 32 x half> %v
|
|
}
|
|
|
|
define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_0(<vscale x 1 x half> %subvec) {
|
|
; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_0:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> undef, <vscale x 1 x half> %subvec, i64 0)
|
|
ret <vscale x 32 x half> %v
|
|
}
|
|
|
|
define <vscale x 32 x half> @insert_nxv32f16_undef_nxv1f16_26(<vscale x 1 x half> %subvec) {
|
|
; CHECK-LABEL: insert_nxv32f16_undef_nxv1f16_26:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: srli a1, a0, 3
|
|
; CHECK-NEXT: srli a0, a0, 2
|
|
; CHECK-NEXT: add a1, a0, a1
|
|
; CHECK-NEXT: vsetvli zero, a1, e16, m1, ta, ma
|
|
; CHECK-NEXT: vslideup.vx v14, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half> undef, <vscale x 1 x half> %subvec, i64 26)
|
|
ret <vscale x 32 x half> %v
|
|
}
|
|
|
|
define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_0(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) {
|
|
; CHECK-LABEL: insert_nxv32i1_nxv8i1_0:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: srli a0, a0, 3
|
|
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
|
|
; CHECK-NEXT: vmv.v.v v0, v8
|
|
; CHECK-NEXT: ret
|
|
%vec = call <vscale x 32 x i1> @llvm.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 0)
|
|
ret <vscale x 32 x i1> %vec
|
|
}
|
|
|
|
define <vscale x 32 x i1> @insert_nxv32i1_nxv8i1_8(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv) {
|
|
; CHECK-LABEL: insert_nxv32i1_nxv8i1_8:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: srli a0, a0, 3
|
|
; CHECK-NEXT: add a1, a0, a0
|
|
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
|
|
; CHECK-NEXT: vslideup.vx v0, v8, a0
|
|
; CHECK-NEXT: ret
|
|
%vec = call <vscale x 32 x i1> @llvm.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1> %v, <vscale x 8 x i1> %sv, i64 8)
|
|
ret <vscale x 32 x i1> %vec
|
|
}
|
|
|
|
define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_0(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) {
|
|
; CHECK-LABEL: insert_nxv4i1_nxv1i1_0:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vmv.v.i v9, 0
|
|
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, mf8, ta, ma
|
|
; CHECK-NEXT: vmv.v.i v10, 0
|
|
; CHECK-NEXT: vmv1r.v v0, v8
|
|
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: srli a0, a0, 3
|
|
; CHECK-NEXT: vsetvli zero, a0, e8, mf2, tu, ma
|
|
; CHECK-NEXT: vmv.v.v v9, v8
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vmsne.vi v0, v9, 0
|
|
; CHECK-NEXT: ret
|
|
%vec = call <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 0)
|
|
ret <vscale x 4 x i1> %vec
|
|
}
|
|
|
|
define <vscale x 4 x i1> @insert_nxv4i1_nxv1i1_2(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv) {
|
|
; CHECK-LABEL: insert_nxv4i1_nxv1i1_2:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vmv.v.i v9, 0
|
|
; CHECK-NEXT: vmerge.vim v9, v9, 1, v0
|
|
; CHECK-NEXT: csrr a0, vlenb
|
|
; CHECK-NEXT: srli a1, a0, 3
|
|
; CHECK-NEXT: srli a0, a0, 2
|
|
; CHECK-NEXT: add a1, a0, a1
|
|
; CHECK-NEXT: vsetvli a2, zero, e8, mf8, ta, ma
|
|
; CHECK-NEXT: vmv.v.i v10, 0
|
|
; CHECK-NEXT: vmv1r.v v0, v8
|
|
; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
|
|
; CHECK-NEXT: vsetvli zero, a1, e8, mf2, tu, ma
|
|
; CHECK-NEXT: vslideup.vx v9, v8, a0
|
|
; CHECK-NEXT: vsetvli a0, zero, e8, mf2, ta, ma
|
|
; CHECK-NEXT: vmsne.vi v0, v9, 0
|
|
; CHECK-NEXT: ret
|
|
%vec = call <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1> %v, <vscale x 1 x i1> %sv, i64 2)
|
|
ret <vscale x 4 x i1> %vec
|
|
}
|
|
|
|
declare <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64>, <vscale x 8 x i64>, i64)
|
|
|
|
define void @insert_nxv8i64_nxv16i64(<vscale x 8 x i64> %sv0, <vscale x 8 x i64> %sv1, <vscale x 16 x i64>* %out) {
|
|
; CHECK-LABEL: insert_nxv8i64_nxv16i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vs8r.v v8, (a0)
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: slli a1, a1, 3
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: vs8r.v v16, (a0)
|
|
; CHECK-NEXT: ret
|
|
%v0 = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
|
|
%v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> %v0, <vscale x 8 x i64> %sv1, i64 8)
|
|
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
|
|
ret void
|
|
}
|
|
|
|
define void @insert_nxv8i64_nxv16i64_lo(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
|
|
; CHECK-LABEL: insert_nxv8i64_nxv16i64_lo:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vs8r.v v8, (a0)
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 0)
|
|
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
|
|
ret void
|
|
}
|
|
|
|
define void @insert_nxv8i64_nxv16i64_hi(<vscale x 8 x i64> %sv0, <vscale x 16 x i64>* %out) {
|
|
; CHECK-LABEL: insert_nxv8i64_nxv16i64_hi:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: csrr a1, vlenb
|
|
; CHECK-NEXT: slli a1, a1, 3
|
|
; CHECK-NEXT: add a0, a0, a1
|
|
; CHECK-NEXT: vs8r.v v8, (a0)
|
|
; CHECK-NEXT: ret
|
|
%v = call <vscale x 16 x i64> @llvm.vector.insert.nxv8i64.nxv16i64(<vscale x 16 x i64> undef, <vscale x 8 x i64> %sv0, i64 8)
|
|
store <vscale x 16 x i64> %v, <vscale x 16 x i64>* %out
|
|
ret void
|
|
}
|
|
|
|
; We should be able to widen the <3 x i64> subvector to a <4 x i64> here because
|
|
; we know that the minimum vscale is 2
|
|
define <vscale x 2 x i64> @insert_nxv2i64_nxv3i64(<3 x i64> %sv) #0 {
|
|
; CHECK-LABEL: insert_nxv2i64_nxv3i64:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: ret
|
|
%vec = call <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v3i64(<vscale x 2 x i64> undef, <3 x i64> %sv, i64 0)
|
|
ret <vscale x 2 x i64> %vec
|
|
}
|
|
|
|
attributes #0 = { vscale_range(2,1024) }
|
|
|
|
declare <vscale x 4 x i1> @llvm.vector.insert.nxv1i1.nxv4i1(<vscale x 4 x i1>, <vscale x 1 x i1>, i64)
|
|
declare <vscale x 32 x i1> @llvm.vector.insert.nxv8i1.nxv32i1(<vscale x 32 x i1>, <vscale x 8 x i1>, i64)
|
|
|
|
declare <vscale x 16 x i8> @llvm.vector.insert.nxv1i8.nxv16i8(<vscale x 16 x i8>, <vscale x 1 x i8>, i64)
|
|
|
|
declare <vscale x 32 x half> @llvm.vector.insert.nxv1f16.nxv32f16(<vscale x 32 x half>, <vscale x 1 x half>, i64)
|
|
declare <vscale x 32 x half> @llvm.vector.insert.nxv2f16.nxv32f16(<vscale x 32 x half>, <vscale x 2 x half>, i64)
|
|
|
|
declare <vscale x 4 x i8> @llvm.vector.insert.nxv1i8.nxv4i8(<vscale x 4 x i8>, <vscale x 1 x i8>, i64 %idx)
|
|
|
|
declare <vscale x 8 x i32> @llvm.vector.insert.nxv2i32.nxv8i32(<vscale x 8 x i32>, <vscale x 2 x i32>, i64 %idx)
|
|
declare <vscale x 8 x i32> @llvm.vector.insert.nxv4i32.nxv8i32(<vscale x 8 x i32>, <vscale x 4 x i32>, i64 %idx)
|
|
|
|
declare <vscale x 16 x i32> @llvm.vector.insert.nxv1i32.nxv16i32(<vscale x 16 x i32>, <vscale x 1 x i32>, i64 %idx)
|
|
declare <vscale x 16 x i32> @llvm.vector.insert.nxv2i32.nxv16i32(<vscale x 16 x i32>, <vscale x 2 x i32>, i64 %idx)
|
|
declare <vscale x 16 x i32> @llvm.vector.insert.nxv4i32.nxv16i32(<vscale x 16 x i32>, <vscale x 4 x i32>, i64 %idx)
|
|
declare <vscale x 16 x i32> @llvm.vector.insert.nxv8i32.nxv16i32(<vscale x 16 x i32>, <vscale x 8 x i32>, i64 %idx)
|
|
|
|
declare <vscale x 2 x i64> @llvm.vector.insert.nxv2i64.v3i64(<vscale x 2 x i64>, <3 x i64>, i64 %idx)
|