e01e711c64
Summary: When expanding the PseudoTail in expandFunctionCall() we were using X6 to save the return address. Since this is a tail call the return address is not needed, this patch replaces it with X0 to be ignored. This matches the behaviour listed in the ISA V2.2 document page 110. tail offset -----> jalr x0, x6, offset GCC exhibits the same behavior. Reviewers: apazos, asb, mgrang Reviewed By: asb Subscribers: rbar, johnrusso, simoncook, niosHD, kito-cheng, shiva0217, zzheng, edward-jones, rogfer01 Differential Revision: https://reviews.llvm.org/D48343 llvm-svn: 335239
274 lines
9.7 KiB
C++
274 lines
9.7 KiB
C++
//===-- RISCVMCCodeEmitter.cpp - Convert RISCV code to machine code -------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file implements the RISCVMCCodeEmitter class.
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//
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/RISCVBaseInfo.h"
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#include "MCTargetDesc/RISCVFixupKinds.h"
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#include "MCTargetDesc/RISCVMCExpr.h"
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#include "MCTargetDesc/RISCVMCTargetDesc.h"
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#include "llvm/ADT/Statistic.h"
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#include "llvm/MC/MCAsmInfo.h"
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#include "llvm/MC/MCCodeEmitter.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCInstBuilder.h"
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#include "llvm/MC/MCInstrInfo.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSymbol.h"
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#include "llvm/Support/Casting.h"
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#include "llvm/Support/EndianStream.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "mccodeemitter"
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STATISTIC(MCNumEmitted, "Number of MC instructions emitted");
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STATISTIC(MCNumFixups, "Number of MC fixups created");
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namespace {
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class RISCVMCCodeEmitter : public MCCodeEmitter {
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RISCVMCCodeEmitter(const RISCVMCCodeEmitter &) = delete;
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void operator=(const RISCVMCCodeEmitter &) = delete;
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MCContext &Ctx;
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MCInstrInfo const &MCII;
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public:
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RISCVMCCodeEmitter(MCContext &ctx, MCInstrInfo const &MCII)
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: Ctx(ctx), MCII(MCII) {}
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~RISCVMCCodeEmitter() override {}
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void encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const override;
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void expandFunctionCall(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// TableGen'erated function for getting the binary encoding for an
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/// instruction.
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uint64_t getBinaryCodeForInstr(const MCInst &MI,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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/// Return binary encoding of operand. If the machine operand requires
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/// relocation, record the relocation and return zero.
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unsigned getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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unsigned getImmOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const;
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};
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} // end anonymous namespace
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MCCodeEmitter *llvm::createRISCVMCCodeEmitter(const MCInstrInfo &MCII,
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const MCRegisterInfo &MRI,
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MCContext &Ctx) {
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return new RISCVMCCodeEmitter(Ctx, MCII);
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}
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// Expand PseudoCALL and PseudoTAIL to AUIPC and JALR with relocation types.
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// We expand PseudoCALL and PseudoTAIL while encoding, meaning AUIPC and JALR
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// won't go through RISCV MC to MC compressed instruction transformation. This
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// is acceptable because AUIPC has no 16-bit form and C_JALR have no immediate
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// operand field. We let linker relaxation deal with it. When linker
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// relaxation enabled, AUIPC and JALR have chance relax to JAL. If C extension
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// is enabled, JAL has chance relax to C_JAL.
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void RISCVMCCodeEmitter::expandFunctionCall(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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MCInst TmpInst;
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MCOperand Func = MI.getOperand(0);
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unsigned Ra = (MI.getOpcode() == RISCV::PseudoTAIL) ? RISCV::X6 : RISCV::X1;
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uint32_t Binary;
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assert(Func.isExpr() && "Expected expression");
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const MCExpr *Expr = Func.getExpr();
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// Create function call expression CallExpr for AUIPC.
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const MCExpr *CallExpr =
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RISCVMCExpr::create(Expr, RISCVMCExpr::VK_RISCV_CALL, Ctx);
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// Emit AUIPC Ra, Func with R_RISCV_CALL relocation type.
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TmpInst = MCInstBuilder(RISCV::AUIPC)
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.addReg(Ra)
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.addOperand(MCOperand::createExpr(CallExpr));
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Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write(OS, Binary, support::little);
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if (MI.getOpcode() == RISCV::PseudoTAIL)
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// Emit JALR X0, X6, 0
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TmpInst = MCInstBuilder(RISCV::JALR).addReg(RISCV::X0).addReg(Ra).addImm(0);
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else
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// Emit JALR X1, X1, 0
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TmpInst = MCInstBuilder(RISCV::JALR).addReg(Ra).addReg(Ra).addImm(0);
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Binary = getBinaryCodeForInstr(TmpInst, Fixups, STI);
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support::endian::write(OS, Binary, support::little);
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}
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void RISCVMCCodeEmitter::encodeInstruction(const MCInst &MI, raw_ostream &OS,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCInstrDesc &Desc = MCII.get(MI.getOpcode());
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// Get byte count of instruction.
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unsigned Size = Desc.getSize();
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if (MI.getOpcode() == RISCV::PseudoCALL ||
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MI.getOpcode() == RISCV::PseudoTAIL) {
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expandFunctionCall(MI, OS, Fixups, STI);
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MCNumEmitted += 2;
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return;
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}
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switch (Size) {
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default:
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llvm_unreachable("Unhandled encodeInstruction length!");
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case 2: {
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uint16_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
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support::endian::write<uint16_t>(OS, Bits, support::little);
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break;
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}
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case 4: {
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uint32_t Bits = getBinaryCodeForInstr(MI, Fixups, STI);
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support::endian::write(OS, Bits, support::little);
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break;
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}
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}
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++MCNumEmitted; // Keep track of the # of mi's emitted.
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}
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unsigned
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RISCVMCCodeEmitter::getMachineOpValue(const MCInst &MI, const MCOperand &MO,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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if (MO.isReg())
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return Ctx.getRegisterInfo()->getEncodingValue(MO.getReg());
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if (MO.isImm())
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return static_cast<unsigned>(MO.getImm());
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llvm_unreachable("Unhandled expression!");
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return 0;
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}
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unsigned
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RISCVMCCodeEmitter::getImmOpValueAsr1(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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const MCOperand &MO = MI.getOperand(OpNo);
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if (MO.isImm()) {
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unsigned Res = MO.getImm();
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assert((Res & 1) == 0 && "LSB is non-zero");
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return Res >> 1;
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}
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return getImmOpValue(MI, OpNo, Fixups, STI);
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}
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unsigned RISCVMCCodeEmitter::getImmOpValue(const MCInst &MI, unsigned OpNo,
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SmallVectorImpl<MCFixup> &Fixups,
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const MCSubtargetInfo &STI) const {
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bool EnableRelax = STI.getFeatureBits()[RISCV::FeatureRelax];
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const MCOperand &MO = MI.getOperand(OpNo);
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MCInstrDesc const &Desc = MCII.get(MI.getOpcode());
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unsigned MIFrm = Desc.TSFlags & RISCVII::InstFormatMask;
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// If the destination is an immediate, there is nothing to do
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if (MO.isImm())
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return MO.getImm();
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assert(MO.isExpr() &&
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"getImmOpValue expects only expressions or immediates");
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const MCExpr *Expr = MO.getExpr();
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MCExpr::ExprKind Kind = Expr->getKind();
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RISCV::Fixups FixupKind = RISCV::fixup_riscv_invalid;
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if (Kind == MCExpr::Target) {
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const RISCVMCExpr *RVExpr = cast<RISCVMCExpr>(Expr);
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switch (RVExpr->getKind()) {
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case RISCVMCExpr::VK_RISCV_None:
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case RISCVMCExpr::VK_RISCV_Invalid:
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llvm_unreachable("Unhandled fixup kind!");
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case RISCVMCExpr::VK_RISCV_LO:
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if (MIFrm == RISCVII::InstFormatI)
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FixupKind = RISCV::fixup_riscv_lo12_i;
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else if (MIFrm == RISCVII::InstFormatS)
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FixupKind = RISCV::fixup_riscv_lo12_s;
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else
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llvm_unreachable("VK_RISCV_LO used with unexpected instruction format");
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break;
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case RISCVMCExpr::VK_RISCV_HI:
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FixupKind = RISCV::fixup_riscv_hi20;
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break;
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case RISCVMCExpr::VK_RISCV_PCREL_LO:
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if (MIFrm == RISCVII::InstFormatI)
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FixupKind = RISCV::fixup_riscv_pcrel_lo12_i;
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else if (MIFrm == RISCVII::InstFormatS)
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FixupKind = RISCV::fixup_riscv_pcrel_lo12_s;
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else
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llvm_unreachable(
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"VK_RISCV_PCREL_LO used with unexpected instruction format");
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break;
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case RISCVMCExpr::VK_RISCV_PCREL_HI:
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FixupKind = RISCV::fixup_riscv_pcrel_hi20;
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break;
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case RISCVMCExpr::VK_RISCV_CALL:
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FixupKind = RISCV::fixup_riscv_call;
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break;
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}
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} else if (Kind == MCExpr::SymbolRef &&
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cast<MCSymbolRefExpr>(Expr)->getKind() == MCSymbolRefExpr::VK_None) {
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if (Desc.getOpcode() == RISCV::JAL) {
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FixupKind = RISCV::fixup_riscv_jal;
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} else if (MIFrm == RISCVII::InstFormatB) {
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FixupKind = RISCV::fixup_riscv_branch;
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} else if (MIFrm == RISCVII::InstFormatCJ) {
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FixupKind = RISCV::fixup_riscv_rvc_jump;
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} else if (MIFrm == RISCVII::InstFormatCB) {
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FixupKind = RISCV::fixup_riscv_rvc_branch;
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}
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}
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assert(FixupKind != RISCV::fixup_riscv_invalid && "Unhandled expression!");
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Fixups.push_back(
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MCFixup::create(0, Expr, MCFixupKind(FixupKind), MI.getLoc()));
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++MCNumFixups;
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if (EnableRelax) {
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if (FixupKind == RISCV::fixup_riscv_call) {
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Fixups.push_back(
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MCFixup::create(0, Expr, MCFixupKind(RISCV::fixup_riscv_relax),
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MI.getLoc()));
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++MCNumFixups;
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}
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}
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return 0;
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}
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#include "RISCVGenMCCodeEmitter.inc"
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