257d5b5639
For RISC-V it is desirable to have relaxation happen in the linker once addresses are known, and as such the size between two instructions/byte sequences in a section could change. For most assembler expressions, this is fine, as the absolute address results in the expression being converted to a fixup, and finally relocations. However, for expressions such as .quad .L2-.L1, the assembler folds this down to a constant once fragments are laid out, under the assumption that the difference can no longer change, although in the case of linker relaxation the differences can change at link time, so the constant is incorrect. One place where this commonly appears is in debug information, where the size of a function expression is in a form similar to the above. This patch extends the assembler to allow an AsmBackend to declare that it does not want the assembler to fold down this expression, and instead generate a pair of relocations that allow the linker to carry out the calculation. In this case, the expression is not folded, but when it comes to emitting a fixup, the generic FK_Data_* fixups are converted into a pair, one for the addition half, one for the subtraction, and this is passed to the relocation generating methods as usual. I have named these FK_Data_Add_* and FK_Data_Sub_* to indicate which half these are for. For RISC-V, which supports this via e.g. the R_RISCV_ADD64, R_RISCV_SUB64 pair of relocations, these are also set to always emit relocations relative to local symbols rather than section offsets. This is to deal with the fact that if relocations were calculated on e.g. .text+8 and .text+4, the result 12 would be stored rather than 4 as both addends are added in the linker. Differential Revision: https://reviews.llvm.org/D45181 Patch by Simon Cook. llvm-svn: 333079
122 lines
3.4 KiB
C++
122 lines
3.4 KiB
C++
//===-- RISCVMCExpr.cpp - RISCV specific MC expression classes ------------===//
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//
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// The LLVM Compiler Infrastructure
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//
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// This file is distributed under the University of Illinois Open Source
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// License. See LICENSE.TXT for details.
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains the implementation of the assembly expression modifiers
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// accepted by the RISCV architecture (e.g. ":lo12:", ":gottprel_g1:", ...).
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//
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//===----------------------------------------------------------------------===//
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#include "RISCV.h"
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#include "RISCVMCExpr.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/MC/MCStreamer.h"
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#include "llvm/MC/MCSymbolELF.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/Object/ELF.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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#define DEBUG_TYPE "riscvmcexpr"
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const RISCVMCExpr *RISCVMCExpr::create(const MCExpr *Expr, VariantKind Kind,
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MCContext &Ctx) {
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return new (Ctx) RISCVMCExpr(Expr, Kind);
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}
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void RISCVMCExpr::printImpl(raw_ostream &OS, const MCAsmInfo *MAI) const {
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bool HasVariant =
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((getKind() != VK_RISCV_None) && (getKind() != VK_RISCV_CALL));
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if (HasVariant)
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OS << '%' << getVariantKindName(getKind()) << '(';
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Expr->print(OS, MAI);
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if (HasVariant)
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OS << ')';
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}
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bool RISCVMCExpr::evaluateAsRelocatableImpl(MCValue &Res,
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const MCAsmLayout *Layout,
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const MCFixup *Fixup) const {
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if (!getSubExpr()->evaluateAsRelocatable(Res, Layout, Fixup))
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return false;
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// Some custom fixup types are not valid with symbol difference expressions
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if (Res.getSymA() && Res.getSymB()) {
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switch (getKind()) {
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default:
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return true;
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case VK_RISCV_LO:
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case VK_RISCV_HI:
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case VK_RISCV_PCREL_LO:
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case VK_RISCV_PCREL_HI:
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return false;
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}
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}
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return true;
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}
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void RISCVMCExpr::visitUsedExpr(MCStreamer &Streamer) const {
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Streamer.visitUsedExpr(*getSubExpr());
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}
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RISCVMCExpr::VariantKind RISCVMCExpr::getVariantKindForName(StringRef name) {
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return StringSwitch<RISCVMCExpr::VariantKind>(name)
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.Case("lo", VK_RISCV_LO)
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.Case("hi", VK_RISCV_HI)
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.Case("pcrel_lo", VK_RISCV_PCREL_LO)
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.Case("pcrel_hi", VK_RISCV_PCREL_HI)
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.Default(VK_RISCV_Invalid);
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}
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StringRef RISCVMCExpr::getVariantKindName(VariantKind Kind) {
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switch (Kind) {
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default:
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llvm_unreachable("Invalid ELF symbol kind");
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case VK_RISCV_LO:
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return "lo";
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case VK_RISCV_HI:
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return "hi";
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case VK_RISCV_PCREL_LO:
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return "pcrel_lo";
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case VK_RISCV_PCREL_HI:
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return "pcrel_hi";
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}
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}
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bool RISCVMCExpr::evaluateAsConstant(int64_t &Res) const {
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MCValue Value;
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if (Kind == VK_RISCV_PCREL_HI || Kind == VK_RISCV_PCREL_LO ||
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Kind == VK_RISCV_CALL)
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return false;
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if (!getSubExpr()->evaluateAsRelocatable(Value, nullptr, nullptr))
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return false;
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if (!Value.isAbsolute())
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return false;
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Res = evaluateAsInt64(Value.getConstant());
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return true;
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}
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int64_t RISCVMCExpr::evaluateAsInt64(int64_t Value) const {
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switch (Kind) {
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default:
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llvm_unreachable("Invalid kind");
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case VK_RISCV_LO:
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return SignExtend64<12>(Value);
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case VK_RISCV_HI:
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// Add 1 if bit 11 is 1, to compensate for low 12 bits being negative.
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return ((Value + 0x800) >> 12) & 0xfffff;
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}
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}
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