Justin Hibbits 4fa4fa6a73 Complete the SPE instruction set patterns ...

This is the lead-up to having SPE codegen.  Add the rest of the
instructions, along with MC tests.

Differential Revision:  https://reviews.llvm.org/D44829

llvm-svn: 337346

2018-07-18 04:24:57 +00:00

..

AArch64

Follow up of r336913: forgot to add the new test files.

2018-07-12 14:59:02 +00:00

AMDGPU

AMDGPU: Fix v_dot{4, 8}* instruction encoding

2018-05-15 19:32:47 +00:00

ARC

[ARC] Add LImm support for J/JL

2018-04-13 15:10:34 +00:00

ARM

[AArch64][ARM] Armv8.4-A: Trace synchronization barrier instruction

2018-07-06 08:03:12 +00:00

Hexagon

NFC - Various typo fixes in tests

2018-07-04 13:28:39 +00:00

Lanai

[lanai] Add Lanai backend.

2016-03-28 13:09:54 +00:00

Mips

[mips] Correct the predicates of arithmetic and logic instructions.

2018-05-30 11:33:35 +00:00

PowerPC

Complete the SPE instruction set patterns

2018-07-18 04:24:57 +00:00

Sparc

This change adds co-processor condition branching and conditional traps to the Sparc back-end.

2016-03-09 18:20:21 +00:00

SystemZ

[SystemZ] Add support for IBM z14 processor (3/3)

2017-07-17 17:44:20 +00:00

WebAssembly

[WebAssembly] Modified tablegen defs to have 2 parallel instuction sets.

2018-06-18 21:22:44 +00:00

X86

[X86][Disassembler] Fix LOCK prefix disassembler support

2018-07-05 23:32:42 +00:00

XCore

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