Luke Lau df387661c4

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565) ...

If I understand correctly there was a point where we used to need this
before it was implied by Zvl*b.

Now that it is though and we use -mattr=+v in pretty much every test we
can remove it.

In unroll-in-loop-vectorizer.ll we can force a VF of 1 instead by using
-force-vector-width=1, and in scalable-basics.ll the two RUN lines were
the same so I merged them.

2025-07-14 21:59:35 +08:00

..

bf16.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

blend-any-of-reduction-cost.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

blocks-with-dead-instructions.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

dead-ops-cost.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

defaults.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

divrem.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

evl-compatible-loops.ll

[VPlan] Support VPWidenIntOrFpInductionRecipes with EVL tail folding (#144666)

2025-07-01 12:29:24 +01:00

evl-iv-simplify.ll

[LV][EVL] Introduce the EVLIndVarSimplify Pass for EVL-vectorized loops (#131005)

2025-05-14 13:49:50 -07:00

f16.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

first-order-recurrence-scalable-vf1.ll

[LoopVectorize] Vectorize fixed-order recurrence with vscale x 1. (#142772)

2025-06-18 16:03:20 +08:00

fminimumnum.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

force-vect-msg.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

illegal-type.ll

[VPlan] Don't access canonical IV in VPWidenPointerInduction::execute.

2025-03-15 21:32:48 +00:00

induction-costs.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

inloop-reduction.ll

[VPlan] Don't convert VPWidenSelectRecipes to vp.select in EVL transform (#146695)

2025-07-03 11:50:25 +01:00

interleaved-accesses-zve32x.ll

…

interleaved-accesses.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

interleaved-cost.ll

[RISCV] Add +optimized-nfN-segment-load-store (#114414)

2024-11-04 06:43:58 +08:00

interleaved-masked-access.ll

[VPlan] Don't convert VPWidenSelectRecipes to vp.select in EVL transform (#146695)

2025-07-03 11:50:25 +01:00

lit.local.cfg

…

lmul.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

low-trip-count.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

mask-index-type.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

masked_gather_scatter.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

only-compute-cost-for-vplan-vfs.ll

[VPlan] Support VPWidenIntOrFpInductionRecipes with EVL tail folding (#144666)

2025-07-01 12:29:24 +01:00

ordered-reduction.ll

[VPlan] Remove no-op SCALAR-STEPS after unrolling. (#123655)

2025-03-25 12:57:24 +00:00

partial-reduce-dot-product.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

pr87378-vpinstruction-or-drop-poison-generating-flags.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

pr88802.ll

[LV] Stengthen loop-invariance checks in isPredicatedInst (#140744)

2025-06-20 14:01:48 +01:00

preserve-dbg-loc.ll

[VPlan] Don't convert VPWidenSelectRecipes to vp.select in EVL transform (#146695)

2025-07-03 11:50:25 +01:00

reg-usage-bf16.ll

[LV] Fix MVE regression from #132190 (#141736)

2025-06-16 09:58:03 +01:00

reg-usage-f16.ll

[LV] Fix MVE regression from #132190 (#141736)

2025-06-16 09:58:03 +01:00

reg-usage.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

remark-reductions.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

riscv-interleaved.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

riscv-unroll.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

riscv-vector-reverse-output.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

riscv-vector-reverse.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

safe-dep-distance.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

scalable-basics.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

scalable-reductions.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

scalable-tailfold.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

scalable-vf-hint.ll

…

select-cmp-reduction.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

select-invariant-cond-cost.ll

[VPlan] Also check if plan for best legacy VF contains simplifications.

2024-11-08 20:53:03 +00:00

short-trip-count.ll

[VPlan] Use InstSimplifyFolder instead of TargetFolder (#141222)

2025-05-28 11:00:14 +02:00

strided-accesses.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

tail-folding-cost.ll

[LoopVectorize] Add cost of generating tail-folding mask to the loop (#130565)

2025-03-21 09:24:56 +00:00

truncate-to-minimal-bitwidth-cost.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

truncate-to-minimal-bitwidth-evl-crash.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

type-info-cache-evl-crash.ll

[VPlan] Don't convert VPWidenSelectRecipes to vp.select in EVL transform (#146695)

2025-07-03 11:50:25 +01:00

uniform-load-store.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

unroll-in-loop-vectorizer.ll

[RISCV] Remove -riscv-v-vector-bits-min from LoopVectorize tests. NFC (#148565)

2025-07-14 21:59:35 +08:00

veclib-function-calls.ll

[RISCV][SLEEF]: Support SLEEF vector library for RISC-V target. (#114014)

2024-11-26 12:25:54 +03:00

vectorize-force-tail-with-evl-bin-unary-ops-args.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

vectorize-force-tail-with-evl-call-intrinsics.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963)

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-cast-intrinsics.ll

[VPlan] Support VPWidenIntOrFpInductionRecipes with EVL tail folding (#144666)

2025-07-01 12:29:24 +01:00

vectorize-force-tail-with-evl-cond-reduction.ll

[VPlan] Don't convert VPWidenSelectRecipes to vp.select in EVL transform (#146695)

2025-07-03 11:50:25 +01:00

vectorize-force-tail-with-evl-div.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

vectorize-force-tail-with-evl-fixed-order-recurrence.ll

[VPlan] Fix first-order splices without header mask not using EVL (#146672)

2025-07-03 16:55:00 +01:00

vectorize-force-tail-with-evl-gather-scatter.ll

[VPlan] Support VPWidenIntOrFpInductionRecipes with EVL tail folding (#144666)

2025-07-01 12:29:24 +01:00

vectorize-force-tail-with-evl-inloop-reduction.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963)

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-interleave.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963)

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-intermediate-store.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963)

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-iv32.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963)

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-known-no-overflow.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963)

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-masked-loadstore.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963)

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-no-masking.ll

…

vectorize-force-tail-with-evl-ordered-reduction.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963)

2025-06-20 11:37:27 -07:00

vectorize-force-tail-with-evl-reduction-cost.ll

[LoopVectorize][NFC] Disable output for tests that don't need it (#124747)

2025-01-29 08:09:50 +00:00

vectorize-force-tail-with-evl-reduction.ll

[VPlan] Don't convert VPWidenSelectRecipes to vp.select in EVL transform (#146695)

2025-07-03 11:50:25 +01:00

vectorize-force-tail-with-evl-reverse-load-store.ll

[VPlan] Emit VPVectorEndPointerRecipe for reverse interleave pointer adjustment (#144864)

2025-07-02 18:16:02 +08:00

vectorize-force-tail-with-evl-safe-dep-distance.ll

[LLVM][IRBuilder] Use NUW arithmetic for Create{ElementCount,TypeSize}. (#143532)

2025-06-19 13:24:39 +01:00

vectorize-force-tail-with-evl-uniform-store.ll

[VPlan] Emit VPVectorEndPointerRecipe for reverse interleave pointer adjustment (#144864)

2025-07-02 18:16:02 +08:00

vectorize-vp-intrinsics.ll

[LV] Consider whether vscale is a known power of two for iteration check (#144963)

2025-06-20 11:37:27 -07:00

vf-will-not-generate-any-vector-insts.ll

[VPlan] Add incoming values for all predecessor to ResumePHI (NFCI).

2025-02-09 11:20:20 +00:00

vplan-vp-call-intrinsics.ll

[VPlan] Replace all uses of VF when EVL tail folding. NFCI (#146339)

2025-06-30 13:47:38 +01:00

vplan-vp-cast-intrinsics.ll

[VPlan] Support VPWidenIntOrFpInductionRecipes with EVL tail folding (#144666)

2025-07-01 12:29:24 +01:00

vplan-vp-intrinsics-fixed-order-recurrence.ll

[VPlan] Use EMIT-SCALAR when printing casts.

2025-06-21 10:23:53 +01:00

vplan-vp-intrinsics-reduction.ll

[VPlan] Replace all uses of VF when EVL tail folding. NFCI (#146339)

2025-06-30 13:47:38 +01:00

vplan-vp-intrinsics.ll

[VPlan] Replace all uses of VF when EVL tail folding. NFCI (#146339)

2025-06-30 13:47:38 +01:00

zvl32b.ll

[RISCV] Disable fixed length vectors with Zve32* without Zvl64b. (#102405)

2024-08-08 09:17:43 -07:00