351d398a37
Dissolving the hierarchical VPlan CFG and converting abstract to concrete recipes can expose additional simplification opportunities. Do a final run of simplifyRecipes before executing the VPlan.
61 lines
2.8 KiB
LLVM
61 lines
2.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --check-globals none --version 5
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; RUN: opt -p loop-vectorize -force-vector-interleave=1 -force-vector-width=4 -S < %s | FileCheck %s
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define void @neg_cond(ptr noalias %p, ptr noalias %q) {
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; CHECK-LABEL: define void @neg_cond(
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; CHECK-SAME: ptr noalias [[P:%.*]], ptr noalias [[Q:%.*]]) {
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; CHECK-NEXT: [[ENTRY:.*:]]
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; CHECK-NEXT: br i1 false, label %[[SCALAR_PH:.*]], label %[[VECTOR_PH:.*]]
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; CHECK: [[VECTOR_PH]]:
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; CHECK-NEXT: br label %[[VECTOR_BODY:.*]]
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; CHECK: [[VECTOR_BODY]]:
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; CHECK-NEXT: [[INDEX:%.*]] = phi i32 [ 0, %[[VECTOR_PH]] ], [ [[INDEX_NEXT:%.*]], %[[VECTOR_BODY]] ]
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; CHECK-NEXT: [[TMP0:%.*]] = getelementptr i32, ptr [[P]], i32 [[INDEX]]
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; CHECK-NEXT: [[WIDE_LOAD:%.*]] = load <4 x i32>, ptr [[TMP0]], align 4
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; CHECK-NEXT: [[TMP3:%.*]] = icmp ne <4 x i32> [[WIDE_LOAD]], splat (i32 42)
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; CHECK-NEXT: [[TMP4:%.*]] = select <4 x i1> [[TMP3]], <4 x i32> splat (i32 42), <4 x i32> splat (i32 43)
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; CHECK-NEXT: store <4 x i32> [[TMP4]], ptr [[TMP0]], align 4
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; CHECK-NEXT: [[INDEX_NEXT]] = add nuw i32 [[INDEX]], 4
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; CHECK-NEXT: [[TMP5:%.*]] = icmp eq i32 [[INDEX_NEXT]], 1024
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; CHECK-NEXT: br i1 [[TMP5]], label %[[MIDDLE_BLOCK:.*]], label %[[VECTOR_BODY]], !llvm.loop [[LOOP0:![0-9]+]]
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; CHECK: [[MIDDLE_BLOCK]]:
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; CHECK-NEXT: br label %[[EXIT:.*]]
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; CHECK: [[SCALAR_PH]]:
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; CHECK-NEXT: br label %[[LOOP:.*]]
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; CHECK: [[LOOP]]:
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; CHECK-NEXT: [[IV:%.*]] = phi i32 [ 0, %[[SCALAR_PH]] ], [ [[IV_NEXT:%.*]], %[[LOOP]] ]
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; CHECK-NEXT: [[P_GEP:%.*]] = getelementptr i32, ptr [[P]], i32 [[IV]]
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; CHECK-NEXT: [[X:%.*]] = load i32, ptr [[P_GEP]], align 4
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; CHECK-NEXT: [[Q_GEP:%.*]] = getelementptr i32, ptr [[Q]], i32 [[IV]]
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; CHECK-NEXT: [[Y:%.*]] = load i32, ptr [[Q_GEP]], align 4
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; CHECK-NEXT: [[CMP:%.*]] = icmp eq i32 [[X]], 42
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; CHECK-NEXT: [[NOT:%.*]] = xor i1 [[CMP]], true
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; CHECK-NEXT: [[SEL:%.*]] = select i1 [[NOT]], i32 42, i32 43
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; CHECK-NEXT: store i32 [[SEL]], ptr [[P_GEP]], align 4
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; CHECK-NEXT: [[IV_NEXT]] = add i32 [[IV]], 1
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; CHECK-NEXT: [[DONE:%.*]] = icmp eq i32 [[IV_NEXT]], 1024
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; CHECK-NEXT: br i1 [[DONE]], label %[[EXIT]], label %[[LOOP]], !llvm.loop [[LOOP3:![0-9]+]]
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; CHECK: [[EXIT]]:
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; CHECK-NEXT: ret void
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;
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entry:
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br label %loop
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loop:
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%iv = phi i32 [0, %entry], [%iv.next, %loop]
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%p.gep = getelementptr i32, ptr %p, i32 %iv
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%x = load i32, ptr %p.gep
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%q.gep = getelementptr i32, ptr %q, i32 %iv
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%y = load i32, ptr %q.gep
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%cmp = icmp eq i32 %x, 42
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%not = xor i1 %cmp, 1
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%sel = select i1 %not, i32 42, i32 43
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store i32 %sel, ptr %p.gep
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%iv.next = add i32 %iv, 1
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%done = icmp eq i32 %iv.next, 1024
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br i1 %done, label %exit, label %loop
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exit:
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ret void
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}
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