David Green d2a9ec29d0 [ARM] MVE bitwise instruction patterns ...

This adds patterns for the simpler VAND, VORR and VEOR bitwise vector
instructions. It also adjusts the top16Zero PatLeaf to not match on vector
instructions, which can otherwise cause problems.

Code written by David Sherwood.

Differential Revision: https://reviews.llvm.org/D63867

llvm-svn: 365113

2019-07-04 08:41:23 +00:00

..

AArch64

[GlobalISel][AArch64] Use getConstantVRegValWithLookThrough for selectArithImmed

2019-07-03 17:46:23 +00:00

AMDGPU

GlobalISel: Fix widenScalar for pointer typed G_MERGE_VALUES

2019-07-03 23:08:06 +00:00

ARC

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ARM

[ARM] Thumb2: favor R4-R7 over R12/LR in allocation order when opt for minsize

2019-07-03 09:58:52 +00:00

AVR

[AVR] Fix tests after r363757

2019-07-04 06:12:47 +00:00

BPF

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Generic

Revert "r364412 [ExpandMemCmp][MergeICmps] Move passes out of CodeGen into opt pipeline."

2019-06-26 12:13:13 +00:00

Hexagon

[Hexagon] Custom-lower UADDO(x, 1) and USUBO(x, 1)

2019-07-01 15:50:09 +00:00

Inputs

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Lanai

[Lanai] auto-generate complete test checks; NFC

2019-06-28 20:45:32 +00:00

Mips

[MIPS GlobalISel] Select integer to floating point conversions

2019-06-20 09:05:02 +00:00

MIR

[AMDGPU] Enable serializing of argument info.

2019-07-03 02:00:21 +00:00

MSP430

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NVPTX

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PowerPC

[PowerPC] Support constraint code "ww"

2019-07-04 04:44:42 +00:00

RISCV

[RISCV] Add RISCV-specific TargetTransformInfo

2019-06-21 13:36:09 +00:00

SPARC

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SystemZ

Allow matching extend-from-memory with strict FP nodes

2019-06-26 17:19:12 +00:00

Thumb

[ARM] Fix unwind info for Thumb1 functions that save high registers.

2019-07-02 21:35:15 +00:00

Thumb2

[ARM] MVE bitwise instruction patterns

2019-07-04 08:41:23 +00:00

WebAssembly

[WebAssembly] Enable IndirectBrExpandPass

2019-07-03 23:54:06 +00:00

WinCFGuard

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WinEH

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X86

[X86] Update test; NFC

2019-07-03 17:45:24 +00:00

XCore

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