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llvm-project/llvm/test/CodeGen
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Konstantin Schwarz d2e66d7fa4 [GlobalISel] Add a combine for and(load , mask) -> zextload 
This only handles simple masks, not shifted masks, for now.

Reviewed By: aemerson

Differential Revision: https://reviews.llvm.org/D109357
2021-09-16 10:42:46 +02:00
..
AArch64
[GlobalISel] Add a combine for and(load , mask) -> zextload
2021-09-16 10:42:46 +02:00
AMDGPU
[GlobalISel] Add a combine for and(load , mask) -> zextload
2021-09-16 10:42:46 +02:00
ARC
[ARC] Improve code generated for i32 ADDC/ADDE and SUBC/SUBE
2021-09-10 13:04:08 -07:00
ARM
autogen a test for ease of update
2021-09-15 11:11:07 -07:00
AVR
[AVR] emit 'MCSA_Global' references to '__do_global_ctors' and '__do_global_dtors'
2021-08-05 10:37:36 +08:00
BPF
[OpaquePtr] Forbid mixing typed and opaque pointers
2021-09-10 15:18:23 +02:00
Generic
Moved the test to X86 as it's x86 specific.
2021-08-31 14:48:29 -04:00
Hexagon
DAG: Fix incorrect folding of fmul -1 to fneg
2021-09-14 21:25:02 -04:00
Inputs
…
Lanai
[Lanai] implement wide immediate support
2021-09-10 10:54:43 +00:00
M68k
[M68k][test] Migrate the remaining fixup and relaxation tests
2021-09-04 16:27:13 -07:00
Mips
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
MIR
AMDGPU: Invert ABI attribute handling
2021-09-09 18:24:28 -04:00
MSP430
…
NVPTX
[NVPTX] Simplify and generalize constant printer.
2021-09-09 11:30:19 -07:00
PowerPC
DAG: Fix incorrect folding of fmul -1 to fneg
2021-09-14 21:25:02 -04:00
RISCV
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
SPARC
…
SystemZ
SystemZ: Tidy up a mir test
2021-08-10 13:56:54 -04:00
Thumb
[ARM] Implement target hook function to decide folding (mul (add x, c1), c2)
2021-09-07 15:42:43 +08:00
Thumb2
RegAllocGreedy: Account for reserved registers in num regs heuristic
2021-09-14 21:00:29 -04:00
VE
…
WebAssembly
Revert "[WebAssembly] Rethrow longjmp in EH handling if EmSjLj is enabled"
2021-09-14 12:59:42 -07:00
WinCFGuard
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WinEH
Fix SEH table addresses for Windows
2021-08-20 22:32:12 +03:00
X86
[X86] combineX86ShuffleChain - ensure we only peek through bitcasts to vectors (PR51858)
2021-09-15 10:21:05 +01:00
XCore
…