d3589edafc
`Data` now references the first byte of the fixup offset within the current fragment. MCAssembler::layout asserts that the fixup offset is within either the fixed-size content or the optional variable-size tail, as this is the most the generic code can validate without knowing the target-specific fixup size. Many backends applyFixup assert ``` assert(Offset + Size <= F.getSize() && "Invalid fixup offset!"); ``` This refactoring allows a subsequent change to move the fixed-size content outside of MCSection::ContentStorage, fixing the -fsanitize=pointer-overflow issue of #150846 Pull Request: https://github.com/llvm/llvm-project/pull/151724
264 lines
8.5 KiB
C++
264 lines
8.5 KiB
C++
//===-- M68kAsmBackend.cpp - M68k Assembler Backend -------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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///
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/// \file
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/// This file contains definitions for M68k assembler backend.
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///
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//===----------------------------------------------------------------------===//
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#include "MCTargetDesc/M68kBaseInfo.h"
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#include "MCTargetDesc/M68kFixupKinds.h"
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#include "llvm/ADT/StringSwitch.h"
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#include "llvm/BinaryFormat/ELF.h"
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#include "llvm/BinaryFormat/MachO.h"
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#include "llvm/MC/MCAsmBackend.h"
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#include "llvm/MC/MCAssembler.h"
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#include "llvm/MC/MCELFObjectWriter.h"
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#include "llvm/MC/MCExpr.h"
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#include "llvm/MC/MCInst.h"
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#include "llvm/MC/MCMachObjectWriter.h"
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#include "llvm/MC/MCObjectWriter.h"
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#include "llvm/MC/MCRegisterInfo.h"
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#include "llvm/MC/MCSectionCOFF.h"
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#include "llvm/MC/MCSectionELF.h"
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#include "llvm/MC/MCSectionMachO.h"
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#include "llvm/MC/MCSubtargetInfo.h"
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#include "llvm/MC/MCValue.h"
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#include "llvm/MC/TargetRegistry.h"
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#include "llvm/Support/Debug.h"
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#include "llvm/Support/ErrorHandling.h"
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#include "llvm/Support/MathExtras.h"
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#include "llvm/Support/raw_ostream.h"
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using namespace llvm;
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#define DEBUG_TYPE "M68k-asm-backend"
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namespace {
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class M68kAsmBackend : public MCAsmBackend {
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bool Allows32BitBranch;
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public:
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M68kAsmBackend(const Target &T, const MCSubtargetInfo &STI)
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: MCAsmBackend(llvm::endianness::big),
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Allows32BitBranch(llvm::StringSwitch<bool>(STI.getCPU())
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.CasesLower("m68020", "m68030", "m68040", true)
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.Default(false)) {}
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void applyFixup(const MCFragment &, const MCFixup &, const MCValue &,
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uint8_t *Data, uint64_t Value, bool IsResolved) override;
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bool mayNeedRelaxation(unsigned Opcode, ArrayRef<MCOperand> Operands,
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const MCSubtargetInfo &STI) const override;
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bool fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t Value) const override;
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void relaxInstruction(MCInst &Inst,
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const MCSubtargetInfo &STI) const override;
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/// Returns the minimum size of a nop in bytes on this target. The assembler
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/// will use this to emit excess padding in situations where the padding
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/// required for simple alignment would be less than the minimum nop size.
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unsigned getMinimumNopSize() const override { return 2; }
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/// Write a sequence of optimal nops to the output, covering \p Count bytes.
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/// \return - true on success, false on failure
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bool writeNopData(raw_ostream &OS, uint64_t Count,
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const MCSubtargetInfo *STI) const override;
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};
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} // end anonymous namespace
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void M68kAsmBackend::applyFixup(const MCFragment &F, const MCFixup &Fixup,
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const MCValue &Target, uint8_t *Data,
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uint64_t Value, bool IsResolved) {
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if (!IsResolved)
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Asm->getWriter().recordRelocation(F, Fixup, Target, Value);
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unsigned Size = 1 << getFixupKindLog2Size(Fixup.getKind());
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assert(Fixup.getOffset() + Size <= F.getSize() && "Invalid fixup offset!");
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// Check that uppper bits are either all zeros or all ones.
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// Specifically ignore overflow/underflow as long as the leakage is
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// limited to the lower bits. This is to remain compatible with
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// other assemblers.
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assert(isIntN(Size * 8 + 1, static_cast<int64_t>(Value)) &&
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"Value does not fit in the Fixup field");
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// Write in Big Endian
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for (unsigned i = 0; i != Size; ++i)
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Data[i] = uint8_t(static_cast<int64_t>(Value) >> ((Size - i - 1) * 8));
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}
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/// cc—Carry clear GE—Greater than or equal
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/// LS—Lower or same PL—Plus
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/// CS—Carry set GT—Greater than
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/// LT—Less than
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/// EQ—Equal HI—Higher
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/// MI—Minus VC—Overflow clear
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/// LE—Less than or equal
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/// NE—Not equal VS—Overflow set
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static unsigned getRelaxedOpcodeBranch(unsigned Op) {
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switch (Op) {
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default:
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return Op;
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// 8 -> 16
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case M68k::BRA8:
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return M68k::BRA16;
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case M68k::Bcc8:
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return M68k::Bcc16;
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case M68k::Bls8:
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return M68k::Bls16;
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case M68k::Blt8:
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return M68k::Blt16;
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case M68k::Beq8:
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return M68k::Beq16;
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case M68k::Bmi8:
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return M68k::Bmi16;
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case M68k::Bne8:
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return M68k::Bne16;
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case M68k::Bge8:
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return M68k::Bge16;
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case M68k::Bcs8:
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return M68k::Bcs16;
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case M68k::Bpl8:
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return M68k::Bpl16;
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case M68k::Bgt8:
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return M68k::Bgt16;
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case M68k::Bhi8:
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return M68k::Bhi16;
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case M68k::Bvc8:
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return M68k::Bvc16;
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case M68k::Ble8:
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return M68k::Ble16;
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case M68k::Bvs8:
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return M68k::Bvs16;
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// 16 -> 32
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case M68k::BRA16:
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return M68k::BRA32;
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case M68k::Bcc16:
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return M68k::Bcc32;
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case M68k::Bls16:
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return M68k::Bls32;
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case M68k::Blt16:
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return M68k::Blt32;
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case M68k::Beq16:
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return M68k::Beq32;
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case M68k::Bmi16:
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return M68k::Bmi32;
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case M68k::Bne16:
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return M68k::Bne32;
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case M68k::Bge16:
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return M68k::Bge32;
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case M68k::Bcs16:
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return M68k::Bcs32;
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case M68k::Bpl16:
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return M68k::Bpl32;
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case M68k::Bgt16:
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return M68k::Bgt32;
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case M68k::Bhi16:
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return M68k::Bhi32;
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case M68k::Bvc16:
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return M68k::Bvc32;
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case M68k::Ble16:
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return M68k::Ble32;
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case M68k::Bvs16:
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return M68k::Bvs32;
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}
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}
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static unsigned getRelaxedOpcode(unsigned Opcode) {
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// NOTE there will be some relaxations for PCD and ARD mem for x20
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return getRelaxedOpcodeBranch(Opcode);
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}
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bool M68kAsmBackend::mayNeedRelaxation(unsigned Opcode, ArrayRef<MCOperand>,
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const MCSubtargetInfo &STI) const {
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// Branches can always be relaxed in either mode.
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return getRelaxedOpcode(Opcode) != Opcode;
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// NOTE will change for x20 mem
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}
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bool M68kAsmBackend::fixupNeedsRelaxation(const MCFixup &Fixup,
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uint64_t UnsignedValue) const {
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int64_t Value = static_cast<int64_t>(UnsignedValue);
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if (!isInt<32>(Value) || (!Allows32BitBranch && !isInt<16>(Value)))
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llvm_unreachable("Cannot relax the instruction, value does not fit");
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// Relax if the value is too big for a (signed) i8
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// (or signed i16 if 32 bit branches can be used). This means
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// that byte-wide instructions have to matched by default
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unsigned KindLog2Size = getFixupKindLog2Size(Fixup.getKind());
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bool FixupFieldTooSmall = false;
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if (!isInt<8>(Value) && KindLog2Size == 0)
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FixupFieldTooSmall = true;
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else if (!isInt<16>(Value) && KindLog2Size <= 1)
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FixupFieldTooSmall = true;
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// NOTE
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// A branch to the immediately following instruction automatically
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// uses the 16-bit displacement format because the 8-bit
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// displacement field contains $00 (zero offset).
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bool ZeroDisplacementNeedsFixup = Value == 0 && KindLog2Size == 0;
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return ZeroDisplacementNeedsFixup || FixupFieldTooSmall;
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}
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// NOTE Can tblgen help at all here to verify there aren't other instructions
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// we can relax?
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void M68kAsmBackend::relaxInstruction(MCInst &Inst,
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const MCSubtargetInfo &STI) const {
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unsigned RelaxedOp = getRelaxedOpcode(Inst.getOpcode());
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assert(RelaxedOp != Inst.getOpcode());
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Inst.setOpcode(RelaxedOp);
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}
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bool M68kAsmBackend::writeNopData(raw_ostream &OS, uint64_t Count,
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const MCSubtargetInfo *STI) const {
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// Cannot emit NOP with size being not multiple of 16 bits.
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if (Count % 2 != 0)
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return false;
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uint64_t NumNops = Count / 2;
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for (uint64_t i = 0; i != NumNops; ++i) {
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OS << "\x4E\x71";
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}
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return true;
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}
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namespace {
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class M68kELFAsmBackend : public M68kAsmBackend {
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public:
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uint8_t OSABI;
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M68kELFAsmBackend(const Target &T, const MCSubtargetInfo &STI, uint8_t OSABI)
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: M68kAsmBackend(T, STI), OSABI(OSABI) {}
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std::unique_ptr<MCObjectTargetWriter>
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createObjectTargetWriter() const override {
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return createM68kELFObjectWriter(OSABI);
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}
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};
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} // end anonymous namespace
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MCAsmBackend *llvm::createM68kAsmBackend(const Target &T,
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const MCSubtargetInfo &STI,
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const MCRegisterInfo &MRI,
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const MCTargetOptions &Options) {
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const Triple &TheTriple = STI.getTargetTriple();
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uint8_t OSABI = MCELFObjectTargetWriter::getOSABI(TheTriple.getOS());
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return new M68kELFAsmBackend(T, STI, OSABI);
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}
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