shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/test/CodeGen/AMDGPU/llvm.amdgcn.raw.ptr.buffer.load.lds.ll
Krzysztof Drewniak d37141776f
[AMDGPU] Enable volatile and non-temporal for loads to LDS (#153244) 
The primary purpose of this commit is to enable marking loads to LDS
(global.load.lds, buffer.*.load.lds) volatile (using bit 31 of the aux
as with normal buffer loads) and to ensure that their !nontemporal
annotations translate to appropriate settings of te cache control bits.

However, in the process of implementing this feature, we also fixed
- Incorrect handling of buffer loads to LDS in GlobalISel
- Updating the handling of volatile on buffers in SIMemoryLegalizer:
previously, the mapping of address spaces would cause volatile on buffer
loads to be silently dropped on at least gfx10.

---------

Co-authored-by: Matt Arsenault <arsenm2@gmail.com>
2025-10-20 12:42:22 -05:00

153 lines
6.8 KiB
LLVM
Raw Blame History

; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
; RUN: llc -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s --check-prefixes=GCN
; RUN: llc -global-isel -mtriple=amdgcn -mcpu=gfx900 < %s | FileCheck %s --check-prefixes=GCN
declare void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) nocapture, i32 %size, i32 %voffset, i32 %soffset, i32 %offset, i32 %aux)
define amdgpu_ps float @buffer_load_lds_dword(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds) {
; GCN-LABEL: buffer_load_lds_dword:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword off, s[0:3], 0 lds
; GCN-NEXT: buffer_load_dword off, s[0:3], 0 offset:4 glc lds
; GCN-NEXT: buffer_load_dword off, s[0:3], 0 offset:8 slc lds
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ds_read_b32 v0, v0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 0, i32 0, i32 0, i32 0)
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 0, i32 0, i32 4, i32 1)
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 0, i32 0, i32 8, i32 2)
%res = load float, ptr addrspace(3) %lds
ret float %res
}
define amdgpu_ps void @buffer_load_lds_dword_imm_voffset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds) {
; GCN-LABEL: buffer_load_lds_dword_imm_voffset:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: v_mov_b32_e32 v0, 0x800
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword v0, s[0:3], 0 offen lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 2048, i32 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_dword_v_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %voffset) {
; GCN-LABEL: buffer_load_lds_dword_v_offset:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword v0, s[0:3], 0 offen lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %voffset, i32 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_dword_s_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 inreg %soffset) {
; GCN-LABEL: buffer_load_lds_dword_s_offset:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword off, s[0:3], s5 lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 0, i32 %soffset, i32 0, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_dword_vs_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %voffset, i32 inreg %soffset) {
; GCN-LABEL: buffer_load_lds_dword_vs_offset:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword v0, s[0:3], s5 offen lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %voffset, i32 %soffset, i32 0, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_dword_vs_imm_offset(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds, i32 %voffset, i32 inreg %soffset) {
; GCN-LABEL: buffer_load_lds_dword_vs_imm_offset:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword v0, s[0:3], s5 offen offset:2048 lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 %voffset, i32 %soffset, i32 2048, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_ushort(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds) {
; GCN-LABEL: buffer_load_lds_ushort:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: v_mov_b32_e32 v0, 0x800
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_ushort v0, s[0:3], 0 offen lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 2, i32 2048, i32 0, i32 0, i32 0)
ret void
}
define amdgpu_ps void @buffer_load_lds_ubyte(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds) {
; GCN-LABEL: buffer_load_lds_ubyte:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_ubyte off, s[0:3], 0 offset:2048 lds
; GCN-NEXT: s_endpgm
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 1, i32 0, i32 0, i32 2048, i32 0)
ret void
}
define amdgpu_ps float @buffer_load_lds_dword_volatile(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds) {
; GCN-LABEL: buffer_load_lds_dword_volatile:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: s_nop 0
; GCN-NEXT: buffer_load_dword off, s[0:3], 0 glc lds
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: buffer_load_dword off, s[0:3], 0 offset:256 lds
; GCN-NEXT: buffer_load_dword off, s[0:3], 0 offset:512 lds
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ds_read_b32 v0, v0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 0, i32 0, i32 0, i32 2147483648)
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 0, i32 0, i32 256, i32 0)
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 0, i32 0, i32 512, i32 0)
%res = load float, ptr addrspace(3) %lds
ret float %res
}
define amdgpu_ps float @buffer_load_lds_dword_nontemporal(ptr addrspace(8) inreg %rsrc, ptr addrspace(3) inreg %lds) {
; GCN-LABEL: buffer_load_lds_dword_nontemporal:
; GCN: ; %bb.0: ; %main_body
; GCN-NEXT: s_mov_b32 m0, s4
; GCN-NEXT: v_mov_b32_e32 v0, s4
; GCN-NEXT: buffer_load_dword off, s[0:3], 0 glc slc lds
; GCN-NEXT: s_waitcnt vmcnt(0)
; GCN-NEXT: ds_read_b32 v0, v0
; GCN-NEXT: s_waitcnt lgkmcnt(0)
; GCN-NEXT: ; return to shader part epilog
main_body:
call void @llvm.amdgcn.raw.ptr.buffer.load.lds(ptr addrspace(8) %rsrc, ptr addrspace(3) %lds, i32 4, i32 0, i32 0, i32 0, i32 0), !nontemporal !0
%res = load float, ptr addrspace(3) %lds
ret float %res
}
!0 = !{i32 1}
Reference in New Issue View Git Blame Copy Permalink