d41e517748
We use the term "interchangeable instructions" to refer to different operators that have the same meaning (e.g., `add x, 0` is equivalent to `mul x, 1`). Non-constant values are not supported, as they may incur high costs with little benefit. --------- Co-authored-by: Alexey Bataev <a.bataev@gmx.com>
43 lines
1.9 KiB
LLVM
43 lines
1.9 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --version 4
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; RUN: opt -S --passes=slp-vectorizer -mtriple=x86_64-unknown-linux-gnu < %s | FileCheck %s
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define i32 @test() {
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; CHECK-LABEL: define i32 @test() {
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; CHECK-NEXT: entry:
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; CHECK-NEXT: [[A_PROMOTED:%.*]] = load i8, ptr null, align 1
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; CHECK-NEXT: [[TMP10:%.*]] = or i8 [[A_PROMOTED]], 0
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; CHECK-NEXT: [[TMP0:%.*]] = insertelement <4 x i8> poison, i8 [[A_PROMOTED]], i32 0
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; CHECK-NEXT: [[TMP1:%.*]] = shufflevector <4 x i8> [[TMP0]], <4 x i8> poison, <4 x i32> zeroinitializer
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; CHECK-NEXT: [[TMP2:%.*]] = add <4 x i8> [[TMP1]], zeroinitializer
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; CHECK-NEXT: [[TMP5:%.*]] = zext <4 x i8> [[TMP2]] to <4 x i16>
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; CHECK-NEXT: [[TMP6:%.*]] = add <4 x i16> [[TMP5]], <i16 0, i16 -1, i16 0, i16 0>
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; CHECK-NEXT: [[TMP7:%.*]] = call i16 @llvm.vector.reduce.or.v4i16(<4 x i16> [[TMP6]])
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; CHECK-NEXT: [[TMP8:%.*]] = zext i16 [[TMP7]] to i32
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; CHECK-NEXT: [[TMP9:%.*]] = and i32 [[TMP8]], 65535
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; CHECK-NEXT: store i8 [[TMP10]], ptr null, align 1
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; CHECK-NEXT: [[CALL3:%.*]] = tail call i32 (ptr, ...) null(ptr null, i32 [[TMP9]])
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; CHECK-NEXT: ret i32 0
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;
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entry:
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%a.promoted = load i8, ptr null, align 1
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%dec.4 = add i8 %a.promoted, 0
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%conv.i.4 = zext i8 %dec.4 to i32
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%sub.i.4 = add nuw nsw i32 %conv.i.4, 0
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%dec.5 = add i8 %a.promoted, 0
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%conv.i.5 = zext i8 %dec.5 to i32
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%sub.i.5 = add nuw nsw i32 %conv.i.5, 65535
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%0 = or i32 %sub.i.4, %sub.i.5
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%dec.6 = or i8 %a.promoted, 0
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%conv.i.6 = zext i8 %dec.6 to i32
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%sub.i.6 = add nuw nsw i32 %conv.i.6, 0
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%1 = or i32 %0, %sub.i.6
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%dec.7 = or i8 %a.promoted, 0
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%conv.i.7 = zext i8 %dec.7 to i32
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%sub.i.7 = add nuw nsw i32 %conv.i.7, 0
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%2 = or i32 %1, %sub.i.7
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%3 = and i32 %2, 65535
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store i8 %dec.7, ptr null, align 1
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%call3 = tail call i32 (ptr, ...) null(ptr null, i32 %3)
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ret i32 0
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}
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