cd28da390f
[LV] Change loops' interleave count computation A set of microbenchmarks in llvm-test-suite (https://github.com/llvm/llvm-test-suite/pull/56), when tested on a AArch64 platform, demonstrates that loop interleaving is beneficial when the vector loop runs at least twice or when the epilogue loop trip count (TC) is minimal. Therefore, we choose interleaving count (IC) between TC/VF & TC/2*VF (VF = vectorization factor), such that remainder TC for the epilogue loop is minimum while the IC is maximum in case the remainder TC is same for both. The initial tests for this change were submitted in PRs: https://github.com/llvm/llvm-project/pull/70272 and https://github.com/llvm/llvm-project/pull/74689.
282 lines
10 KiB
LLVM
282 lines
10 KiB
LLVM
; RUN: opt < %s -debug-only=loop-vectorize -passes='function(loop-vectorize),default<O2>' -vectorizer-maximize-bandwidth -mtriple=powerpc64-unknown-linux -S -mcpu=pwr8 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-PWR8
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; RUN: opt < %s -debug-only=loop-vectorize -passes='function(loop-vectorize),default<O2>' -vectorizer-maximize-bandwidth -mtriple=powerpc64le-unknown-linux -S -mcpu=pwr9 2>&1 | FileCheck %s --check-prefixes=CHECK,CHECK-PWR9
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; REQUIRES: asserts
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@a = global [1024 x i8] zeroinitializer, align 16
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@b = global [1024 x i8] zeroinitializer, align 16
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define i32 @foo() {
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; CHECK-LABEL: foo
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; CHECK-PWR8: Executing best plan with VF=16, UF=4
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; CHECK-PWR9: Executing best plan with VF=8, UF=8
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entry:
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br label %for.body
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for.cond.cleanup:
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%add.lcssa = phi i32 [ %add, %for.body ]
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ret i32 %add.lcssa
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for.body:
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%s.015 = phi i32 [ 0, %entry ], [ %add, %for.body ]
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%arrayidx = getelementptr inbounds [1024 x i8], ptr @a, i64 0, i64 %indvars.iv
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%0 = load i8, ptr %arrayidx, align 1
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%conv = zext i8 %0 to i32
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%arrayidx2 = getelementptr inbounds [1024 x i8], ptr @b, i64 0, i64 %indvars.iv
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%1 = load i8, ptr %arrayidx2, align 1
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%conv3 = zext i8 %1 to i32
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%sub = sub nsw i32 %conv, %conv3
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%ispos = icmp sgt i32 %sub, -1
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%neg = sub nsw i32 0, %sub
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%2 = select i1 %ispos, i32 %sub, i32 %neg
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%add = add nsw i32 %2, %s.015
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 1024
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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define i32 @goo() {
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; For indvars.iv used in a computating chain only feeding into getelementptr or cmp,
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; it will not have vector version and the vector register usage will not exceed the
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; available vector register number.
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; CHECK-LABEL: goo
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; CHECK: Executing best plan with VF=16, UF=4
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entry:
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br label %for.body
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for.cond.cleanup: ; preds = %for.body
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%add.lcssa = phi i32 [ %add, %for.body ]
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ret i32 %add.lcssa
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%s.015 = phi i32 [ 0, %entry ], [ %add, %for.body ]
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%tmp1 = add nsw i64 %indvars.iv, 3
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%arrayidx = getelementptr inbounds [1024 x i8], ptr @a, i64 0, i64 %tmp1
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%tmp = load i8, ptr %arrayidx, align 1
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%conv = zext i8 %tmp to i32
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%tmp2 = add nsw i64 %indvars.iv, 2
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%arrayidx2 = getelementptr inbounds [1024 x i8], ptr @b, i64 0, i64 %tmp2
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%tmp3 = load i8, ptr %arrayidx2, align 1
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%conv3 = zext i8 %tmp3 to i32
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%sub = sub nsw i32 %conv, %conv3
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%ispos = icmp sgt i32 %sub, -1
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%neg = sub nsw i32 0, %sub
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%tmp4 = select i1 %ispos, i32 %sub, i32 %neg
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%add = add nsw i32 %tmp4, %s.015
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 1024
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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define i64 @bar(ptr nocapture %a) {
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; CHECK-LABEL: bar
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; CHECK: Executing best plan with VF=2, UF=8
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entry:
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br label %for.body
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for.cond.cleanup:
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%add2.lcssa = phi i64 [ %add2, %for.body ]
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ret i64 %add2.lcssa
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for.body:
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%i.012 = phi i64 [ 0, %entry ], [ %inc, %for.body ]
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%s.011 = phi i64 [ 0, %entry ], [ %add2, %for.body ]
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%arrayidx = getelementptr inbounds i64, ptr %a, i64 %i.012
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%0 = load i64, ptr %arrayidx, align 8
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%add = add nsw i64 %0, %i.012
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store i64 %add, ptr %arrayidx, align 8
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%add2 = add nsw i64 %add, %s.011
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%inc = add nuw nsw i64 %i.012, 1
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%exitcond = icmp eq i64 %inc, 1024
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br i1 %exitcond, label %for.cond.cleanup, label %for.body
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}
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@d = external global [0 x i64], align 8
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@e = external global [0 x i32], align 4
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@c = external global [0 x i32], align 4
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define void @hoo(i32 %n) {
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; CHECK-LABEL: hoo
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; CHECK: Executing best plan with VF=1, UF=8
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%indvars.iv = phi i64 [ 0, %entry ], [ %indvars.iv.next, %for.body ]
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%arrayidx = getelementptr inbounds [0 x i64], ptr @d, i64 0, i64 %indvars.iv
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%tmp = load i64, ptr %arrayidx, align 8
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%arrayidx1 = getelementptr inbounds [0 x i32], ptr @e, i64 0, i64 %tmp
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%tmp1 = load i32, ptr %arrayidx1, align 4
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%arrayidx3 = getelementptr inbounds [0 x i32], ptr @c, i64 0, i64 %indvars.iv
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store i32 %tmp1, ptr %arrayidx3, align 4
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 1
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%exitcond = icmp eq i64 %indvars.iv.next, 10000
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret void
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}
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define float @float_(ptr nocapture readonly %a, ptr nocapture readonly %b, i32 %n) {
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;CHECK-LABEL: float_
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;CHECK: LV(REG): VF = 1
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;CHECK: LV(REG): Found max usage: 2 item
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;CHECK-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
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;CHECK-NEXT: LV(REG): RegisterClass: PPC::VSXRC, 3 registers
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;CHECK: LV(REG): Found invariant usage: 1 item
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;CHECK-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 1 registers
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entry:
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%cmp = icmp sgt i32 %n, 0
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br i1 %cmp, label %preheader, label %for.end
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preheader:
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%t0 = sext i32 %n to i64
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br label %for
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for:
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%indvars.iv = phi i64 [ 0, %preheader ], [ %indvars.iv.next, %for ]
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%s.02 = phi float [ 0.0, %preheader ], [ %add4, %for ]
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%arrayidx = getelementptr inbounds float, ptr %a, i64 %indvars.iv
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%t1 = load float, ptr %arrayidx, align 4
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%arrayidx3 = getelementptr inbounds float, ptr %b, i64 %indvars.iv
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%t2 = load float, ptr %arrayidx3, align 4
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%add = fadd fast float %t1, %s.02
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%add4 = fadd fast float %add, %t2
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%indvars.iv.next = add nuw nsw i64 %indvars.iv, 32
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%cmp1 = icmp slt i64 %indvars.iv.next, %t0
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br i1 %cmp1, label %for, label %loopexit
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loopexit:
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%add4.lcssa = phi float [ %add4, %for ]
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br label %for.end
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for.end:
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%s.0.lcssa = phi float [ 0.0, %entry ], [ %add4.lcssa, %loopexit ]
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ret float %s.0.lcssa
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}
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define void @double_(ptr nocapture %A, i32 %n) nounwind uwtable ssp {
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;CHECK-LABEL: double_
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;CHECK-PWR8: LV(REG): VF = 2
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;CHECK-PWR8: LV(REG): Found max usage: 2 item
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;CHECK-PWR8-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
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;CHECK-PWR8-NEXT: LV(REG): RegisterClass: PPC::VSXRC, 5 registers
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;CHECK-PWR8: LV(REG): Found invariant usage: 1 item
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;CHECK-PWR8-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 1 registers
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;CHECK-PWR9: LV(REG): VF = 1
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;CHECK-PWR9: LV(REG): Found max usage: 2 item
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;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
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;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::VSXRC, 5 registers
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;CHECK-PWR9: LV(REG): Found invariant usage: 1 item
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;CHECK-PWR9-NEXT: LV(REG): RegisterClass: PPC::GPRRC, 1 registers
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%1 = sext i32 %n to i64
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br label %2
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; <label>:2 ; preds = %2, %0
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%indvars.iv = phi i64 [ %indvars.iv.next, %2 ], [ %1, %0 ]
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%3 = getelementptr inbounds double, ptr %A, i64 %indvars.iv
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%4 = load double, ptr %3, align 8
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%5 = fadd double %4, 3.000000e+00
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%6 = fmul double %4, 2.000000e+00
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%7 = fadd double %5, %6
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%8 = fadd double %7, 2.000000e+00
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%9 = fmul double %8, 5.000000e-01
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%10 = fadd double %6, %9
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%11 = fsub double %10, %5
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%12 = fadd double %4, %11
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%13 = fdiv double %8, %12
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%14 = fmul double %13, %8
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%15 = fmul double %6, %14
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%16 = fmul double %5, %15
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%17 = fadd double %16, -3.000000e+00
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%18 = fsub double %4, %5
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%19 = fadd double %6, %18
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%20 = fadd double %13, %19
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%21 = fadd double %20, %17
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%22 = fadd double %21, 3.000000e+00
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%23 = fmul double %4, %22
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store double %23, ptr %3, align 8
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%indvars.iv.next = add i64 %indvars.iv, -1
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%24 = trunc i64 %indvars.iv to i32
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%25 = icmp eq i32 %24, 0
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br i1 %25, label %26, label %2
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; <label>:26 ; preds = %2
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ret void
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}
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define ppc_fp128 @fp128_(ptr nocapture %n, ppc_fp128 %d) nounwind readonly {
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;CHECK-LABEL: fp128_
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;CHECK: LV(REG): VF = 1
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;CHECK: LV(REG): Found max usage: 2 item
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;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 2 registers
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;CHECK: LV(REG): RegisterClass: PPC::VRRC, 2 registers
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entry:
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br label %for.body
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for.body: ; preds = %for.body, %entry
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%i.06 = phi i32 [ 0, %entry ], [ %inc, %for.body ]
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%x.05 = phi ppc_fp128 [ %d, %entry ], [ %sub, %for.body ]
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%arrayidx = getelementptr inbounds ppc_fp128, ptr %n, i32 %i.06
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%0 = load ppc_fp128, ptr %arrayidx, align 8
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%sub = fsub fast ppc_fp128 %x.05, %0
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%inc = add nsw i32 %i.06, 1
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%exitcond = icmp eq i32 %inc, 2048
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br i1 %exitcond, label %for.end, label %for.body
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for.end: ; preds = %for.body
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ret ppc_fp128 %sub
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}
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define void @fp16_(ptr nocapture readonly %pIn, ptr nocapture %pOut, i32 %numRows, i32 %numCols, i32 %scale.coerce) #0 {
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;CHECK-LABEL: fp16_
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;CHECK: LV(REG): VF = 1
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;CHECK: LV(REG): Found max usage: 2 item
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;CHECK: LV(REG): RegisterClass: PPC::GPRRC, 4 registers
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;CHECK: LV(REG): RegisterClass: PPC::VSXRC, 2 registers
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entry:
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%tmp.0.extract.trunc = trunc i32 %scale.coerce to i16
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%0 = bitcast i16 %tmp.0.extract.trunc to half
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%mul = mul i32 %numCols, %numRows
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%shr = lshr i32 %mul, 2
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%cmp26 = icmp eq i32 %shr, 0
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br i1 %cmp26, label %while.end, label %while.body
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while.body: ; preds = %entry, %while.body
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%pIn.addr.029 = phi ptr [ %add.ptr, %while.body ], [ %pIn, %entry ]
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%pOut.addr.028 = phi ptr [ %add.ptr7, %while.body ], [ %pOut, %entry ]
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%blkCnt.027 = phi i32 [ %dec, %while.body ], [ %shr, %entry ]
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%1 = load half, ptr %pIn.addr.029, align 2
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%arrayidx2 = getelementptr inbounds half, ptr %pIn.addr.029, i32 1
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%2 = load half, ptr %arrayidx2, align 2
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%mul3 = fmul half %1, %0
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%mul4 = fmul half %2, %0
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store half %mul3, ptr %pOut.addr.028, align 2
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%arrayidx6 = getelementptr inbounds half, ptr %pOut.addr.028, i32 1
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store half %mul4, ptr %arrayidx6, align 2
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%add.ptr = getelementptr inbounds half, ptr %pIn.addr.029, i32 2
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%add.ptr7 = getelementptr inbounds half, ptr %pOut.addr.028, i32 2
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%dec = add nsw i32 %blkCnt.027, -1
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%cmp = icmp eq i32 %dec, 0
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br i1 %cmp, label %while.end, label %while.body
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while.end: ; preds = %while.body, %entry
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ret void
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}
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