eecb99c5f6
These tests rely on SCEV looking recognizing an "or" with no common bits as an "add". Add the disjoint flag to relevant or instructions in preparation for switching SCEV to use the flag instead of the ValueTracking query. The IR with disjoint flag matches what InstCombine would produce.
43 lines
1.4 KiB
LLVM
43 lines
1.4 KiB
LLVM
; REQUIRES: asserts
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; RUN: opt -S -passes=loop-vectorize -force-vector-width=8 -force-vector-interleave=1 -enable-interleaved-mem-accesses -debug-only=loop-vectorize,vectorutils -disable-output < %s 2>&1 | FileCheck %s
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target datalayout = "e-m:e-p:32:32-f64:32:64-f80:32-n8:16:32-S128"
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; Ensure that we don't create interleave groups for predicated
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; strided accesses.
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; CHECK: LV: Checking a loop in 'masked_strided'
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; CHECK: LV: Analyzing interleaved accesses...
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; CHECK-NOT: LV: Creating an interleave group
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define dso_local void @masked_strided(ptr noalias nocapture readonly %p, ptr noalias nocapture %q, i8 zeroext %guard) local_unnamed_addr {
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entry:
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%conv = zext i8 %guard to i32
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br label %for.body
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for.body:
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%ix.017 = phi i32 [ 0, %entry ], [ %inc, %for.inc ]
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%cmp1 = icmp ugt i32 %ix.017, %conv
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br i1 %cmp1, label %if.then, label %for.inc
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if.then:
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%mul = shl nuw nsw i32 %ix.017, 1
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%arrayidx = getelementptr inbounds i8, ptr %p, i32 %mul
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%0 = load i8, ptr %arrayidx, align 1
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%arrayidx4 = getelementptr inbounds i8, ptr %q, i32 %mul
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store i8 %0, ptr %arrayidx4, align 1
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%sub = sub i8 0, %0
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%add = or disjoint i32 %mul, 1
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%arrayidx8 = getelementptr inbounds i8, ptr %q, i32 %add
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store i8 %sub, ptr %arrayidx8, align 1
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br label %for.inc
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for.inc:
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%inc = add nuw nsw i32 %ix.017, 1
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%exitcond = icmp eq i32 %inc, 1024
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br i1 %exitcond, label %for.end, label %for.body
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for.end:
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ret void
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}
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