90ba33099c
This patch canonicalizes getelementptr instructions with constant indices to use the `i8` source element type. This makes it easier for optimizations to recognize that two GEPs are identical, because they don't need to see past many different ways to express the same offset. This is a first step towards https://discourse.llvm.org/t/rfc-replacing-getelementptr-with-ptradd/68699. This is limited to constant GEPs only for now, as they have a clear canonical form, while we're not yet sure how exactly to deal with variable indices. The test llvm/test/Transforms/PhaseOrdering/switch_with_geps.ll gives two representative examples of the kind of optimization improvement we expect from this change. In the first test SimplifyCFG can now realize that all switch branches are actually the same. In the second test it can convert it into simple arithmetic. These are representative of common optimization failures we see in Rust. Fixes https://github.com/llvm/llvm-project/issues/69841.
42 lines
1.8 KiB
LLVM
42 lines
1.8 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py
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; RUN: opt < %s -passes=slp-vectorizer,instcombine -S | FileCheck %s
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; Regression test for a bug in the SLP vectorizer that was causing
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; these rotates to be incorrectly combined into a vector rotate.
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target datalayout = "e-m:e-p:32:32-i64:64-n32:64-S128"
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target triple = "wasm32-unknown-unknown"
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define void @foo(<2 x i64> %x, <4 x i32> %y, ptr %out) #0 {
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; CHECK-LABEL: @foo(
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; CHECK-NEXT: [[A:%.*]] = extractelement <2 x i64> [[X:%.*]], i64 0
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; CHECK-NEXT: [[B:%.*]] = extractelement <4 x i32> [[Y:%.*]], i64 2
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; CHECK-NEXT: [[CONV6:%.*]] = zext i32 [[B]] to i64
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; CHECK-NEXT: [[C:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[A]], i64 [[A]], i64 [[CONV6]])
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; CHECK-NEXT: store i64 [[C]], ptr [[OUT:%.*]], align 8
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; CHECK-NEXT: [[D:%.*]] = extractelement <2 x i64> [[X]], i64 1
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; CHECK-NEXT: [[E:%.*]] = extractelement <4 x i32> [[Y]], i64 3
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; CHECK-NEXT: [[CONV17:%.*]] = zext i32 [[E]] to i64
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; CHECK-NEXT: [[F:%.*]] = tail call i64 @llvm.fshl.i64(i64 [[D]], i64 [[D]], i64 [[CONV17]])
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; CHECK-NEXT: [[ARRAYIDX2:%.*]] = getelementptr inbounds i8, ptr [[OUT]], i32 8
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; CHECK-NEXT: store i64 [[F]], ptr [[ARRAYIDX2]], align 8
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; CHECK-NEXT: ret void
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;
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%a = extractelement <2 x i64> %x, i32 0
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%b = extractelement <4 x i32> %y, i32 2
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%conv6 = zext i32 %b to i64
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%c = tail call i64 @llvm.fshl.i64(i64 %a, i64 %a, i64 %conv6)
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store i64 %c, ptr %out
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%d = extractelement <2 x i64> %x, i32 1
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%e = extractelement <4 x i32> %y, i32 3
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%conv17 = zext i32 %e to i64
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%f = tail call i64 @llvm.fshl.i64(i64 %d, i64 %d, i64 %conv17)
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%arrayidx2 = getelementptr inbounds i64, ptr %out, i32 1
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store i64 %f, ptr %arrayidx2
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ret void
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}
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declare i64 @llvm.fshl.i64(i64, i64, i64)
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attributes #0 = {"target-cpu"="generic" "target-features"="+simd128"}
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