11bf7da64a
The GPUDivergenceAnalysis is now renamed to just "DivergenceAnalysis" since there is no conflict with LegacyDivergenceAnalysis. In the legacy PM, this analysis can only be used through the legacy DA serving as a wrapper. It is now made available as a pass in the new PM, and has no relation with the legacy DA. The new DA currently cannot handle irreducible control flow; its presence can cause the analysis to run indefinitely. The analysis is now modified to detect this and report all instructions in the function as divergent. This is super conservative, but allows the analysis to be used without hanging the compiler. Reviewed By: aeubanks Differential Revision: https://reviews.llvm.org/D96615
111 lines
4.8 KiB
LLVM
111 lines
4.8 KiB
LLVM
; RUN: opt -mtriple=amdgcn-unknown-amdhsa -mcpu=tahiti -enable-new-pm=0 -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s
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; RUN: opt -mtriple=amdgcn-unknown-amdhsa -mcpu=gfx908 -enable-new-pm=0 -analyze -divergence -use-gpu-divergence-analysis %s | FileCheck %s
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; RUN: opt -mtriple amdgcn-unknown-amdhsa -mcpu=tahiti -passes='print<divergence>' -disable-output %s 2>&1 | FileCheck %s
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; RUN: opt -mtriple amdgcn-unknown-amdhsa -mcpu=gfx908 -passes='print<divergence>' -disable-output %s 2>&1 | FileCheck %s
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; Make sure nothing crashes on targets with or without AGPRs
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; CHECK: Divergence Analysis' for function 'inline_asm_1_sgpr_virtreg_output':
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; CHECK-NOT: DIVERGENT
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define i32 @inline_asm_1_sgpr_virtreg_output() {
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%sgpr = call i32 asm "s_mov_b32 $0, 0", "=s"()
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ret i32 %sgpr
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}
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; CHECK: Divergence Analysis' for function 'inline_asm_1_sgpr_physreg_output':
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; CHECK-NOT: DIVERGENT
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define i32 @inline_asm_1_sgpr_physreg_output() {
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%sgpr = call i32 asm "s_mov_b32 s0, 0", "={s0}"()
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ret i32 %sgpr
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}
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; CHECK: Divergence Analysis' for function 'inline_asm_1_vgpr_virtreg_output':
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; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"()
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define i32 @inline_asm_1_vgpr_virtreg_output() {
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%vgpr = call i32 asm "v_mov_b32 $0, 0", "=v"()
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ret i32 %vgpr
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}
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; CHECK: Divergence Analysis' for function 'inline_asm_1_vgpr_physreg_output':
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; CHECK: DIVERGENT: %vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"()
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define i32 @inline_asm_1_vgpr_physreg_output() {
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%vgpr = call i32 asm "v_mov_b32 v0, 0", "={v0}"()
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ret i32 %vgpr
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}
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; CHECK: Divergence Analysis' for function 'inline_asm_1_agpr_virtreg_output':
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; CHECK: DIVERGENT: %vgpr = call i32 asm "; def $0", "=a"()
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define i32 @inline_asm_1_agpr_virtreg_output() {
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%vgpr = call i32 asm "; def $0", "=a"()
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ret i32 %vgpr
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}
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; CHECK: Divergence Analysis' for function 'inline_asm_1_agpr_physreg_output':
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; CHECK: DIVERGENT: %vgpr = call i32 asm "; def a0", "={a0}"()
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define i32 @inline_asm_1_agpr_physreg_output() {
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%vgpr = call i32 asm "; def a0", "={a0}"()
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ret i32 %vgpr
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}
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; CHECK: Divergence Analysis' for function 'inline_asm_2_sgpr_virtreg_output':
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; CHECK-NOT: DIVERGENT
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define void @inline_asm_2_sgpr_virtreg_output() {
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%asm = call { i32, i32 } asm "; def $0, $1", "=s,=s"()
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%sgpr0 = extractvalue { i32, i32 } %asm, 0
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%sgpr1 = extractvalue { i32, i32 } %asm, 1
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store i32 %sgpr0, i32 addrspace(1)* undef
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store i32 %sgpr1, i32 addrspace(1)* undef
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ret void
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}
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; One output is SGPR, one is VGPR. Infer divergent for the aggregate, but uniform on the SGPR extract
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; CHECK: Divergence Analysis' for function 'inline_asm_sgpr_vgpr_virtreg_output':
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; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=s,=v"()
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; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 0
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; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 1
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define void @inline_asm_sgpr_vgpr_virtreg_output() {
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%asm = call { i32, i32 } asm "; def $0, $1", "=s,=v"()
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%sgpr = extractvalue { i32, i32 } %asm, 0
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%vgpr = extractvalue { i32, i32 } %asm, 1
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store i32 %sgpr, i32 addrspace(1)* undef
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store i32 %vgpr, i32 addrspace(1)* undef
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ret void
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}
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; CHECK: Divergence Analysis' for function 'inline_asm_vgpr_sgpr_virtreg_output':
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; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s"()
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; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 0
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; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 1
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define void @inline_asm_vgpr_sgpr_virtreg_output() {
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%asm = call { i32, i32 } asm "; def $0, $1", "=v,=s"()
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%vgpr = extractvalue { i32, i32 } %asm, 0
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%sgpr = extractvalue { i32, i32 } %asm, 1
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store i32 %vgpr, i32 addrspace(1)* undef
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store i32 %sgpr, i32 addrspace(1)* undef
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ret void
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}
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; Have an extra output constraint
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; CHECK: Divergence Analysis' for function 'multi_sgpr_inline_asm_output_input_constraint':
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; CHECK-NOT: DIVERGENT
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define void @multi_sgpr_inline_asm_output_input_constraint() {
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%asm = call { i32, i32 } asm "; def $0, $1", "=s,=s,s"(i32 1234)
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%sgpr0 = extractvalue { i32, i32 } %asm, 0
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%sgpr1 = extractvalue { i32, i32 } %asm, 1
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store i32 %sgpr0, i32 addrspace(1)* undef
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store i32 %sgpr1, i32 addrspace(1)* undef
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ret void
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}
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; CHECK: Divergence Analysis' for function 'inline_asm_vgpr_sgpr_virtreg_output_input_constraint':
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; CHECK: DIVERGENT: %asm = call { i32, i32 } asm "; def $0, $1", "=v,=s,v"(i32 1234)
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; CHECK-NEXT: DIVERGENT: %vgpr = extractvalue { i32, i32 } %asm, 0
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; CHECK-NEXT: {{^[ \t]+}}%sgpr = extractvalue { i32, i32 } %asm, 1
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define void @inline_asm_vgpr_sgpr_virtreg_output_input_constraint() {
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%asm = call { i32, i32 } asm "; def $0, $1", "=v,=s,v"(i32 1234)
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%vgpr = extractvalue { i32, i32 } %asm, 0
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%sgpr = extractvalue { i32, i32 } %asm, 1
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store i32 %vgpr, i32 addrspace(1)* undef
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store i32 %sgpr, i32 addrspace(1)* undef
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ret void
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}
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