Brendan Sweeney 4fd5d935a3

[RISCV] Emitting proper atomic ABI tag when Zalasr is enabled (#121017) ...

When Zalasr is enabled, it will emit the A7 atomic ABI tag. Zalasr is
the load-acquire and store-release extension, and the reason A7 (and
A6S) exists is to support it.

The A7 atomic ABI is compatible with A6S (which is what is currently
emitted as the tag), but A7 is not compatible with A6C, while A6C and
A6S are compatible.


https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-atomic.adoc#risc-v-atomics-mappings


https://github.com/riscv-non-isa/riscv-elf-psabi-doc/blob/master/riscv-elf.adoc#tag_riscv_atomic_abi-14-uleb128version

2025-03-03 11:34:52 -08:00

..

AArch64

[AArch64] Don't try to custom lower fp16 selects with nofp (#129492)

2025-03-03 15:50:11 +00:00

AMDGPU

[AMDGPU] Set inst_pref_size to maximum (#126981)

2025-03-03 10:40:31 -08:00

ARC

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ARM

[CodeGen][NewPM] Port MachineSink to NPM (#115434)

2025-03-03 15:49:37 +05:30

AVR

PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)

2025-02-05 23:29:02 +07:00

BPF

PeepholeOpt: Fix looking for def of current copy to coalesce (#125533)

2025-02-05 23:29:02 +07:00

CSKY

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DirectX

[DirectX] Support the CBufferLoadLegacy operation (#128699)

2025-02-26 09:43:30 -08:00

Generic

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Hexagon

[CodeGen][NewPM] Port MachineSink to NPM (#115434)

2025-03-03 15:49:37 +05:30

Inputs

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Lanai

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LoongArch

[LoongArch] use TypeWidenVector for most illegal vector types (#126456)

2025-03-03 10:26:11 +08:00

M68k

[M68k] always use movem for register spills (#106715)

2025-01-31 19:42:40 -06:00

Mips

[Mips] Reserve hardware register HWR2 (#127775)

2025-02-20 20:53:30 +08:00

MIR

[win] Enable test/CodeGen/MIR/AArch64 on Windows (#122832)

2025-03-03 09:54:28 -08:00

MLRegAlloc

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MSP430

[SelectionDAG] Utilizing target hook convertSelectOfConstantsToMath for SelectwithConstant (#127599)

2025-02-25 20:32:24 +05:30

NVPTX

[NVPTX] Add Intrinsics for discard.* (#128404)

2025-03-03 22:53:49 +05:30

PowerPC

[PowerPC] hoist xxspltib out of loop body (#127121)

2025-03-03 11:14:02 -05:00

RISCV

[RISCV] Emitting proper atomic ABI tag when Zalasr is enabled (#121017)

2025-03-03 11:34:52 -08:00

SPARC

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

SPIRV

[SPIR-V] Prevent type change of GEP results in type inference (#129250)

2025-02-28 20:55:14 +01:00

SystemZ

[CodeGen][NewPM] Port MachineSink to NPM (#115434)

2025-03-03 15:49:37 +05:30

Thumb

[RegAlloc][NewPM] Plug Greedy RA in codegen pipeline (#120557)

2025-03-03 11:06:15 +05:30

Thumb2

PeepholeOpt: Immediately check if a reg_sequence compose supports a subregister (#128279)

2025-02-26 10:15:17 +07:00

VE

[CodeGen] Use __extendhfsf2 and __truncsfhf2 by default (#126880)

2025-02-19 10:16:57 +01:00

WebAssembly

[WebAssemblyLowerEmscriptenEHSjLj] Avoid setting import_name where possible (#128564)

2025-02-26 14:05:00 -08:00

WinCFGuard

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WinEH

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X86

[X86] Generate kmov for masking integers (#120593)

2025-03-03 20:35:09 +05:30

XCore

[llvm] Remove br i1 undef in some llvm/test/CodeGen tests (#126811)

2025-02-12 09:19:00 +00:00

Xtensa

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