hezuoqiang f4ba1db5bf [GlobalISel] Fix the error transformation of BRCOND to BCC ...

Fix https://github.com/llvm/llvm-project/issues/62309

Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D150527

2023-07-13 21:20:01 +08:00

..

AArch64CallLowering.cpp

[AArch64][GlobalISel] IR translate support for a return instruction of type <1 x i8> or <1 x i16> when using GlobalISel.

2023-06-25 14:40:48 -07:00

AArch64CallLowering.h

[AArch64][GlobalISel] Lower formal arguments of AAPCS & ms_abi variadic functions.

2023-02-08 16:29:40 +01:00

AArch64GlobalISelUtils.cpp

[CodeGen] llvm::Optional => std::optional

2022-12-13 09:06:36 +00:00

AArch64GlobalISelUtils.h

[CodeGen] llvm::Optional => std::optional

2022-12-13 09:06:36 +00:00

AArch64InstructionSelector.cpp

[GlobalISel] Fix the error transformation of BRCOND to BCC

2023-07-13 21:20:01 +08:00

AArch64LegalizerInfo.cpp

[GlobalISel] Introduce G_CONSTANT_FOLD_BARRIER and use it to prevent constant folding

2023-06-09 11:45:06 -07:00

AArch64LegalizerInfo.h

[AArch64] Remove unused declaration legalizeShuffleVector

2023-05-29 10:53:45 -07:00

AArch64O0PreLegalizerCombiner.cpp

[AArch64] Use GlobalISel MatchTable Combiner Backend

2023-07-11 11:27:14 +02:00

AArch64PostLegalizerCombiner.cpp

[AArch64] Use GlobalISel MatchTable Combiner Backend

2023-07-11 11:27:14 +02:00

AArch64PostLegalizerLowering.cpp

[AArch64] Split lowerVectorFCMP combine

2023-07-12 13:13:37 +02:00

AArch64PostSelectOptimize.cpp

[AArch64][GlobalISel] Select G_UADDE/G_SADDE/G_USUBE/G_SSUBE

2023-06-25 14:32:00 -07:00

AArch64PreLegalizerCombiner.cpp

[AArch64] Use GlobalISel MatchTable Combiner Backend

2023-07-11 11:27:14 +02:00

AArch64RegisterBankInfo.cpp

[TableGen][GlobalISel] Account for HwMode in RegisterBank register sizes

2023-06-02 23:14:17 -07:00

AArch64RegisterBankInfo.h

[nfc][codegen] Move RegisterBank[Info].h under CodeGen

2022-03-01 21:53:25 -08:00