00786d3a5f
This is intended to behave like GCC's `-mcmodel=extreme`. Technically the true GCC equivalent would be `-mcmodel=large` which is not yet implemented there, and we probably do not want to take the "Large" name until things settle in GCC side, but: * LLVM does not have a `CodeModel::Extreme`, and it seems too early to have such a variant added just for enabling LoongArch; and * `CodeModel::Small` is already being used for GCC `-mcmodel=normal` which is already a case of divergent naming. Regarding the codegen, loads/stores immediately after a PC-relative large address load (that ends with something like `add.d $addr, $addr, $tmp`) should get merged with the addition into corresponding `ldx/stx` ops, but is currently not done. This is because pseudo-instructions are expanded after instruction selection, and is best fixed with a separate change. Reviewed By: SixWeining Differential Revision: https://reviews.llvm.org/D150522
528 lines
20 KiB
C++
528 lines
20 KiB
C++
//===-- LoongArchExpandPseudoInsts.cpp - Expand pseudo instructions -------===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file contains a pass that expands pseudo instructions into target
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// instructions.
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//
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//===----------------------------------------------------------------------===//
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#include "LoongArch.h"
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#include "LoongArchInstrInfo.h"
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#include "LoongArchTargetMachine.h"
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#include "MCTargetDesc/LoongArchBaseInfo.h"
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#include "MCTargetDesc/LoongArchMCTargetDesc.h"
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#include "llvm/CodeGen/LivePhysRegs.h"
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#include "llvm/CodeGen/MachineFunctionPass.h"
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#include "llvm/CodeGen/MachineInstrBuilder.h"
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#include "llvm/CodeGen/MachineOperand.h"
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#include "llvm/CodeGen/Register.h"
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#include "llvm/MC/MCContext.h"
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#include "llvm/Support/CodeGen.h"
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#include "llvm/Support/ErrorHandling.h"
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using namespace llvm;
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#define LOONGARCH_PRERA_EXPAND_PSEUDO_NAME \
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"LoongArch Pre-RA pseudo instruction expansion pass"
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namespace {
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class LoongArchPreRAExpandPseudo : public MachineFunctionPass {
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public:
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const LoongArchInstrInfo *TII;
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static char ID;
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LoongArchPreRAExpandPseudo() : MachineFunctionPass(ID) {
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initializeLoongArchPreRAExpandPseudoPass(*PassRegistry::getPassRegistry());
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}
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bool runOnMachineFunction(MachineFunction &MF) override;
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void getAnalysisUsage(AnalysisUsage &AU) const override {
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AU.setPreservesCFG();
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MachineFunctionPass::getAnalysisUsage(AU);
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}
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StringRef getPassName() const override {
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return LOONGARCH_PRERA_EXPAND_PSEUDO_NAME;
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}
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private:
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bool expandMBB(MachineBasicBlock &MBB);
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bool expandMI(MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandPcalau12iInstPair(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned FlagsHi, unsigned SecondOpcode,
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unsigned FlagsLo);
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bool expandLargeAddressLoad(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned LastOpcode, unsigned IdentifyingMO);
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bool expandLargeAddressLoad(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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unsigned LastOpcode, unsigned IdentifyingMO,
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const MachineOperand &Symbol, Register DestReg,
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bool EraseFromParent);
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bool expandLoadAddressPcrel(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool Large = false);
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bool expandLoadAddressGot(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool Large = false);
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bool expandLoadAddressTLSLE(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI);
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bool expandLoadAddressTLSIE(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool Large = false);
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bool expandLoadAddressTLSLD(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool Large = false);
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bool expandLoadAddressTLSGD(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool Large = false);
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bool expandFunctionCALL(MachineBasicBlock &MBB,
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MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI,
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bool IsTailCall);
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};
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char LoongArchPreRAExpandPseudo::ID = 0;
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bool LoongArchPreRAExpandPseudo::runOnMachineFunction(MachineFunction &MF) {
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TII =
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static_cast<const LoongArchInstrInfo *>(MF.getSubtarget().getInstrInfo());
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bool Modified = false;
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for (auto &MBB : MF)
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Modified |= expandMBB(MBB);
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return Modified;
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}
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bool LoongArchPreRAExpandPseudo::expandMBB(MachineBasicBlock &MBB) {
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bool Modified = false;
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MachineBasicBlock::iterator MBBI = MBB.begin(), E = MBB.end();
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while (MBBI != E) {
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MachineBasicBlock::iterator NMBBI = std::next(MBBI);
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Modified |= expandMI(MBB, MBBI, NMBBI);
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MBBI = NMBBI;
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}
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return Modified;
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}
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bool LoongArchPreRAExpandPseudo::expandMI(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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switch (MBBI->getOpcode()) {
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case LoongArch::PseudoLA_PCREL:
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return expandLoadAddressPcrel(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_PCREL_LARGE:
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return expandLoadAddressPcrel(MBB, MBBI, NextMBBI, /*Large=*/true);
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case LoongArch::PseudoLA_GOT:
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return expandLoadAddressGot(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_GOT_LARGE:
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return expandLoadAddressGot(MBB, MBBI, NextMBBI, /*Large=*/true);
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case LoongArch::PseudoLA_TLS_LE:
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return expandLoadAddressTLSLE(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_TLS_IE:
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return expandLoadAddressTLSIE(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_TLS_IE_LARGE:
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return expandLoadAddressTLSIE(MBB, MBBI, NextMBBI, /*Large=*/true);
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case LoongArch::PseudoLA_TLS_LD:
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return expandLoadAddressTLSLD(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_TLS_LD_LARGE:
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return expandLoadAddressTLSLD(MBB, MBBI, NextMBBI, /*Large=*/true);
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case LoongArch::PseudoLA_TLS_GD:
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return expandLoadAddressTLSGD(MBB, MBBI, NextMBBI);
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case LoongArch::PseudoLA_TLS_GD_LARGE:
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return expandLoadAddressTLSGD(MBB, MBBI, NextMBBI, /*Large=*/true);
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case LoongArch::PseudoCALL:
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return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/false);
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case LoongArch::PseudoTAIL:
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return expandFunctionCALL(MBB, MBBI, NextMBBI, /*IsTailCall=*/true);
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}
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return false;
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}
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bool LoongArchPreRAExpandPseudo::expandPcalau12iInstPair(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, unsigned FlagsHi,
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unsigned SecondOpcode, unsigned FlagsLo) {
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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Register DestReg = MI.getOperand(0).getReg();
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Register ScratchReg =
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MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
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MachineOperand &Symbol = MI.getOperand(1);
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg)
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.addDisp(Symbol, 0, FlagsHi);
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MachineInstr *SecondMI =
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BuildMI(MBB, MBBI, DL, TII->get(SecondOpcode), DestReg)
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.addReg(ScratchReg)
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.addDisp(Symbol, 0, FlagsLo);
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if (MI.hasOneMemOperand())
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SecondMI->addMemOperand(*MF, *MI.memoperands_begin());
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MI.eraseFromParent();
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return true;
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}
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bool LoongArchPreRAExpandPseudo::expandLargeAddressLoad(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, unsigned LastOpcode,
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unsigned IdentifyingMO) {
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MachineInstr &MI = *MBBI;
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return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LastOpcode, IdentifyingMO,
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MI.getOperand(2), MI.getOperand(0).getReg(),
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true);
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}
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bool LoongArchPreRAExpandPseudo::expandLargeAddressLoad(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, unsigned LastOpcode,
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unsigned IdentifyingMO, const MachineOperand &Symbol, Register DestReg,
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bool EraseFromParent) {
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// Code Sequence:
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//
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// Part1: pcalau12i $scratch, %MO1(sym)
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// Part0: addi.d $dest, $zero, %MO0(sym)
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// Part2: lu32i.d $dest, %MO2(sym)
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// Part3: lu52i.d $dest, $dest, %MO3(sym)
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// Fin: LastOpcode $dest, $dest, $scratch
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unsigned MO0, MO1, MO2, MO3;
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switch (IdentifyingMO) {
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default:
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llvm_unreachable("unsupported identifying MO");
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case LoongArchII::MO_PCREL_LO:
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MO0 = IdentifyingMO;
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MO1 = LoongArchII::MO_PCREL_HI;
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MO2 = LoongArchII::MO_PCREL64_LO;
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MO3 = LoongArchII::MO_PCREL64_HI;
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break;
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case LoongArchII::MO_GOT_PC_HI:
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case LoongArchII::MO_LD_PC_HI:
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case LoongArchII::MO_GD_PC_HI:
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// These cases relocate just like the GOT case, except for Part1.
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MO0 = LoongArchII::MO_GOT_PC_LO;
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MO1 = IdentifyingMO;
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MO2 = LoongArchII::MO_GOT_PC64_LO;
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MO3 = LoongArchII::MO_GOT_PC64_HI;
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break;
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case LoongArchII::MO_IE_PC_LO:
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MO0 = IdentifyingMO;
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MO1 = LoongArchII::MO_IE_PC_HI;
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MO2 = LoongArchII::MO_IE_PC64_LO;
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MO3 = LoongArchII::MO_IE_PC64_HI;
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break;
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}
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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assert(MF->getSubtarget<LoongArchSubtarget>().is64Bit() &&
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"Large code model requires LA64");
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Register TmpPart1 =
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MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
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Register TmpPart0 =
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DestReg.isVirtual()
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? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
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: DestReg;
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Register TmpParts02 =
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DestReg.isVirtual()
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? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
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: DestReg;
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Register TmpParts023 =
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DestReg.isVirtual()
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? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
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: DestReg;
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auto Part1 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), TmpPart1);
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auto Part0 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ADDI_D), TmpPart0)
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.addReg(LoongArch::R0);
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auto Part2 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), TmpParts02)
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// "rj" is needed due to InstrInfo pattern requirement.
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.addReg(TmpPart0, RegState::Kill);
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auto Part3 = BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), TmpParts023)
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.addReg(TmpParts02, RegState::Kill);
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BuildMI(MBB, MBBI, DL, TII->get(LastOpcode), DestReg)
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.addReg(TmpParts023)
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.addReg(TmpPart1, RegState::Kill);
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if (Symbol.getType() == MachineOperand::MO_ExternalSymbol) {
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const char *SymName = Symbol.getSymbolName();
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Part0.addExternalSymbol(SymName, MO0);
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Part1.addExternalSymbol(SymName, MO1);
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Part2.addExternalSymbol(SymName, MO2);
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Part3.addExternalSymbol(SymName, MO3);
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} else {
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Part0.addDisp(Symbol, 0, MO0);
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Part1.addDisp(Symbol, 0, MO1);
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Part2.addDisp(Symbol, 0, MO2);
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Part3.addDisp(Symbol, 0, MO3);
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}
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if (EraseFromParent)
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MI.eraseFromParent();
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return true;
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}
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bool LoongArchPreRAExpandPseudo::expandLoadAddressPcrel(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, bool Large) {
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if (Large)
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// Emit the 5-insn large address load sequence with the `%pc` family of
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// relocs.
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return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
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LoongArchII::MO_PCREL_LO);
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// Code Sequence:
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// pcalau12i $rd, %pc_hi20(sym)
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// addi.w/d $rd, $rd, %pc_lo12(sym)
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MachineFunction *MF = MBB.getParent();
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const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
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unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
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return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_PCREL_HI,
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SecondOpcode, LoongArchII::MO_PCREL_LO);
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}
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bool LoongArchPreRAExpandPseudo::expandLoadAddressGot(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, bool Large) {
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if (Large)
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// Emit the 5-insn large address load sequence with the `%got_pc` family
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// of relocs, loading the result from GOT with `ldx.d` in the end.
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return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
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LoongArchII::MO_GOT_PC_HI);
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// Code Sequence:
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// pcalau12i $rd, %got_pc_hi20(sym)
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// ld.w/d $rd, $rd, %got_pc_lo12(sym)
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MachineFunction *MF = MBB.getParent();
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const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
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unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
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return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_GOT_PC_HI,
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SecondOpcode, LoongArchII::MO_GOT_PC_LO);
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}
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bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLE(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI) {
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// Code Sequence:
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// lu12i.w $rd, %le_hi20(sym)
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// ori $rd, $rd, %le_lo12(sym)
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//
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// And additionally if generating code using the large code model:
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//
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// lu32i.d $rd, %le64_lo20(sym)
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// lu52i.d $rd, $rd, %le64_hi12(sym)
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MachineFunction *MF = MBB.getParent();
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MachineInstr &MI = *MBBI;
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DebugLoc DL = MI.getDebugLoc();
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bool Large = MF->getTarget().getCodeModel() == CodeModel::Large;
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Register DestReg = MI.getOperand(0).getReg();
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Register Parts01 =
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Large ? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
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: DestReg;
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Register Part1 =
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MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
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MachineOperand &Symbol = MI.getOperand(1);
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU12I_W), Part1)
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.addDisp(Symbol, 0, LoongArchII::MO_LE_HI);
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::ORI), Parts01)
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.addReg(Part1, RegState::Kill)
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.addDisp(Symbol, 0, LoongArchII::MO_LE_LO);
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if (Large) {
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Register Parts012 =
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MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass);
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU32I_D), Parts012)
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// "rj" is needed due to InstrInfo pattern requirement.
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.addReg(Parts01, RegState::Kill)
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.addDisp(Symbol, 0, LoongArchII::MO_LE64_LO);
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BuildMI(MBB, MBBI, DL, TII->get(LoongArch::LU52I_D), DestReg)
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.addReg(Parts012, RegState::Kill)
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.addDisp(Symbol, 0, LoongArchII::MO_LE64_HI);
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}
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MI.eraseFromParent();
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return true;
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}
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bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSIE(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, bool Large) {
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if (Large)
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// Emit the 5-insn large address load sequence with the `%ie_pc` family
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// of relocs, loading the result with `ldx.d` in the end.
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return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::LDX_D,
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LoongArchII::MO_IE_PC_LO);
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// Code Sequence:
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// pcalau12i $rd, %ie_pc_hi20(sym)
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// ld.w/d $rd, $rd, %ie_pc_lo12(sym)
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MachineFunction *MF = MBB.getParent();
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const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
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unsigned SecondOpcode = STI.is64Bit() ? LoongArch::LD_D : LoongArch::LD_W;
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return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_IE_PC_HI,
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SecondOpcode, LoongArchII::MO_IE_PC_LO);
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}
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bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSLD(
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MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
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MachineBasicBlock::iterator &NextMBBI, bool Large) {
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if (Large)
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// Emit the 5-insn large address load sequence with the `%got_pc` family
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// of relocs, with the `pcalau12i` insn relocated with `%ld_pc_hi20`.
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return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
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LoongArchII::MO_LD_PC_HI);
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// Code Sequence:
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// pcalau12i $rd, %ld_pc_hi20(sym)
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// addi.w/d $rd, $rd, %got_pc_lo12(sym)
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MachineFunction *MF = MBB.getParent();
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const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
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unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
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return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_LD_PC_HI,
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SecondOpcode, LoongArchII::MO_GOT_PC_LO);
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}
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bool LoongArchPreRAExpandPseudo::expandLoadAddressTLSGD(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI, bool Large) {
|
|
if (Large)
|
|
// Emit the 5-insn large address load sequence with the `%got_pc` family
|
|
// of relocs, with the `pcalau12i` insn relocated with `%gd_pc_hi20`.
|
|
return expandLargeAddressLoad(MBB, MBBI, NextMBBI, LoongArch::ADD_D,
|
|
LoongArchII::MO_GD_PC_HI);
|
|
|
|
// Code Sequence:
|
|
// pcalau12i $rd, %gd_pc_hi20(sym)
|
|
// addi.w/d $rd, $rd, %got_pc_lo12(sym)
|
|
MachineFunction *MF = MBB.getParent();
|
|
const auto &STI = MF->getSubtarget<LoongArchSubtarget>();
|
|
unsigned SecondOpcode = STI.is64Bit() ? LoongArch::ADDI_D : LoongArch::ADDI_W;
|
|
return expandPcalau12iInstPair(MBB, MBBI, NextMBBI, LoongArchII::MO_GD_PC_HI,
|
|
SecondOpcode, LoongArchII::MO_GOT_PC_LO);
|
|
}
|
|
|
|
bool LoongArchPreRAExpandPseudo::expandFunctionCALL(
|
|
MachineBasicBlock &MBB, MachineBasicBlock::iterator MBBI,
|
|
MachineBasicBlock::iterator &NextMBBI, bool IsTailCall) {
|
|
MachineFunction *MF = MBB.getParent();
|
|
MachineInstr &MI = *MBBI;
|
|
DebugLoc DL = MI.getDebugLoc();
|
|
const MachineOperand &Func = MI.getOperand(0);
|
|
MachineInstrBuilder CALL;
|
|
unsigned Opcode;
|
|
|
|
switch (MF->getTarget().getCodeModel()) {
|
|
default:
|
|
report_fatal_error("Unsupported code model");
|
|
break;
|
|
case CodeModel::Small: {
|
|
// CALL:
|
|
// bl func
|
|
// TAIL:
|
|
// b func
|
|
Opcode = IsTailCall ? LoongArch::PseudoB_TAIL : LoongArch::BL;
|
|
CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).add(Func);
|
|
break;
|
|
}
|
|
case CodeModel::Medium: {
|
|
// CALL:
|
|
// pcalau12i $ra, %pc_hi20(func)
|
|
// jirl $ra, $ra, %pc_lo12(func)
|
|
// TAIL:
|
|
// pcalau12i $scratch, %pc_hi20(func)
|
|
// jirl $r0, $scratch, %pc_lo12(func)
|
|
Opcode =
|
|
IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
|
|
Register ScratchReg =
|
|
IsTailCall
|
|
? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
|
|
: LoongArch::R1;
|
|
MachineInstrBuilder MIB =
|
|
BuildMI(MBB, MBBI, DL, TII->get(LoongArch::PCALAU12I), ScratchReg);
|
|
CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(ScratchReg);
|
|
if (Func.isSymbol()) {
|
|
const char *FnName = Func.getSymbolName();
|
|
MIB.addExternalSymbol(FnName, LoongArchII::MO_PCREL_HI);
|
|
CALL.addExternalSymbol(FnName, LoongArchII::MO_PCREL_LO);
|
|
break;
|
|
}
|
|
assert(Func.isGlobal() && "Expected a GlobalValue at this time");
|
|
const GlobalValue *GV = Func.getGlobal();
|
|
MIB.addGlobalAddress(GV, 0, LoongArchII::MO_PCREL_HI);
|
|
CALL.addGlobalAddress(GV, 0, LoongArchII::MO_PCREL_LO);
|
|
break;
|
|
}
|
|
case CodeModel::Large: {
|
|
// Emit the 5-insn large address load sequence, either directly or
|
|
// indirectly in case of going through the GOT, then JIRL_TAIL or
|
|
// JIRL_CALL to $addr.
|
|
Opcode =
|
|
IsTailCall ? LoongArch::PseudoJIRL_TAIL : LoongArch::PseudoJIRL_CALL;
|
|
Register AddrReg =
|
|
IsTailCall
|
|
? MF->getRegInfo().createVirtualRegister(&LoongArch::GPRRegClass)
|
|
: LoongArch::R1;
|
|
|
|
bool UseGOT = Func.isGlobal() && !Func.getGlobal()->isDSOLocal();
|
|
unsigned MO = UseGOT ? LoongArchII::MO_GOT_PC_HI : LoongArchII::MO_PCREL_LO;
|
|
unsigned LAOpcode = UseGOT ? LoongArch::LDX_D : LoongArch::ADD_D;
|
|
expandLargeAddressLoad(MBB, MBBI, NextMBBI, LAOpcode, MO, Func, AddrReg,
|
|
false);
|
|
CALL = BuildMI(MBB, MBBI, DL, TII->get(Opcode)).addReg(AddrReg).addImm(0);
|
|
break;
|
|
}
|
|
}
|
|
|
|
// Transfer implicit operands.
|
|
CALL.copyImplicitOps(MI);
|
|
|
|
// Transfer MI flags.
|
|
CALL.setMIFlags(MI.getFlags());
|
|
|
|
MI.eraseFromParent();
|
|
return true;
|
|
}
|
|
|
|
} // end namespace
|
|
|
|
INITIALIZE_PASS(LoongArchPreRAExpandPseudo, "loongarch-prera-expand-pseudo",
|
|
LOONGARCH_PRERA_EXPAND_PSEUDO_NAME, false, false)
|
|
|
|
namespace llvm {
|
|
|
|
FunctionPass *createLoongArchPreRAExpandPseudoPass() {
|
|
return new LoongArchPreRAExpandPseudo();
|
|
}
|
|
|
|
} // end namespace llvm
|