ca50be8c89
NVPTXAliasAnalysis extends the default AA to take pointer address spaces into account. The analysis assumes that pointers in different address spaces do not alias, unless one of them is generic (flat) address space. The patch also implements pointsToConstantMemory (via getModRefInfoMask) to expose semantic of the constant address space to the optimizer as discussed in D112466. Differential Revision: https://reviews.llvm.org/D124787
109 lines
3.7 KiB
C++
109 lines
3.7 KiB
C++
//===-- NVPTXTargetMachine.h - Define TargetMachine for NVPTX ---*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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//
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// This file declares the NVPTX specific subclass of TargetMachine.
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//
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//===----------------------------------------------------------------------===//
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#ifndef LLVM_LIB_TARGET_NVPTX_NVPTXTARGETMACHINE_H
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#define LLVM_LIB_TARGET_NVPTX_NVPTXTARGETMACHINE_H
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#include "NVPTXSubtarget.h"
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#include "llvm/Target/TargetMachine.h"
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#include <optional>
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#include <utility>
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namespace llvm {
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/// NVPTXTargetMachine
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///
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class NVPTXTargetMachine : public LLVMTargetMachine {
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bool is64bit;
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// Use 32-bit pointers for accessing const/local/short AS.
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bool UseShortPointers;
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std::unique_ptr<TargetLoweringObjectFile> TLOF;
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NVPTX::DrvInterface drvInterface;
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NVPTXSubtarget Subtarget;
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// Hold Strings that can be free'd all together with NVPTXTargetMachine
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BumpPtrAllocator StrAlloc;
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UniqueStringSaver StrPool;
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public:
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NVPTXTargetMachine(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OP,
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bool is64bit);
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~NVPTXTargetMachine() override;
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const NVPTXSubtarget *getSubtargetImpl(const Function &) const override {
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return &Subtarget;
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}
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const NVPTXSubtarget *getSubtargetImpl() const { return &Subtarget; }
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bool is64Bit() const { return is64bit; }
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bool useShortPointers() const { return UseShortPointers; }
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NVPTX::DrvInterface getDrvInterface() const { return drvInterface; }
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UniqueStringSaver &getStrPool() const {
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return const_cast<UniqueStringSaver &>(StrPool);
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}
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TargetPassConfig *createPassConfig(PassManagerBase &PM) override;
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// Emission of machine code through MCJIT is not supported.
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bool addPassesToEmitMC(PassManagerBase &, MCContext *&, raw_pwrite_stream &,
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bool = true) override {
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return true;
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}
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TargetLoweringObjectFile *getObjFileLowering() const override {
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return TLOF.get();
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}
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MachineFunctionInfo *
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createMachineFunctionInfo(BumpPtrAllocator &Allocator, const Function &F,
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const TargetSubtargetInfo *STI) const override;
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void registerDefaultAliasAnalyses(AAManager &AAM) override;
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void registerPassBuilderCallbacks(PassBuilder &PB) override;
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TargetTransformInfo getTargetTransformInfo(const Function &F) const override;
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bool isMachineVerifierClean() const override {
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return false;
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}
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std::pair<const Value *, unsigned>
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getPredicatedAddrSpace(const Value *V) const override;
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}; // NVPTXTargetMachine.
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class NVPTXTargetMachine32 : public NVPTXTargetMachine {
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virtual void anchor();
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public:
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NVPTXTargetMachine32(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
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bool JIT);
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};
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class NVPTXTargetMachine64 : public NVPTXTargetMachine {
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virtual void anchor();
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public:
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NVPTXTargetMachine64(const Target &T, const Triple &TT, StringRef CPU,
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StringRef FS, const TargetOptions &Options,
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std::optional<Reloc::Model> RM,
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std::optional<CodeModel::Model> CM, CodeGenOpt::Level OL,
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bool JIT);
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};
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} // end namespace llvm
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#endif
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