6a35ceaacf
For rv32, we test the legalization of i8, i16 and i32. For rv64, we additionally test the legalization of i64. This is the first of a series of commits aiming to legalize arithmetic instructions for RISCV. Reviewed By: craig.topper, arsenm Differential Revision: https://reviews.llvm.org/D154978
34 lines
1.1 KiB
C++
34 lines
1.1 KiB
C++
//===-- RISCVLegalizerInfo.cpp ----------------------------------*- C++ -*-===//
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//
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// Part of the LLVM Project, under the Apache License v2.0 with LLVM Exceptions.
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// See https://llvm.org/LICENSE.txt for license information.
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// SPDX-License-Identifier: Apache-2.0 WITH LLVM-exception
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//
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//===----------------------------------------------------------------------===//
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/// \file
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/// This file implements the targeting of the Machinelegalizer class for RISC-V.
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/// \todo This should be generated by TableGen.
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//===----------------------------------------------------------------------===//
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#include "RISCVLegalizerInfo.h"
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#include "RISCVSubtarget.h"
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#include "llvm/CodeGen/TargetOpcodes.h"
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#include "llvm/CodeGen/ValueTypes.h"
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#include "llvm/IR/DerivedTypes.h"
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#include "llvm/IR/Type.h"
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using namespace llvm;
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RISCVLegalizerInfo::RISCVLegalizerInfo(const RISCVSubtarget &ST) {
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const unsigned XLen = ST.getXLen();
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const LLT XLenLLT = LLT::scalar(XLen);
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using namespace TargetOpcode;
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getActionDefinitionsBuilder({G_ADD, G_SUB, G_AND, G_OR, G_XOR})
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.legalFor({XLenLLT})
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.clampScalar(0, XLenLLT, XLenLLT);
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getLegacyLegalizerInfo().computeTables();
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}
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