742fb8b5c7
If we have a store of a load with no other uses in between it, it's considered dead and is removed. So sometimes when legalizing a fixed length vector store of an insert, we end up producing better code through scalarization than without. An example is the follow below: %a = load <4 x i64>, ptr %x %b = insertelement <4 x i64> %a, i64 %y, i32 2 store <4 x i64> %b, ptr %x If this is scalarized, then DAGCombine successfully removes 3 of the 4 stores which are considered dead, and on RISC-V we get: sd a1, 16(a0) However if we make the vector type legal (-mattr=+v), then we lose the optimisation because we don't scalarize it. This patch attempts to recover the optimisation for vectors by identifying patterns where we store a load with a single insert inbetween, replacing it with a scalar store of the inserted element. Reviewed By: RKSimon Differential Revision: https://reviews.llvm.org/D152276
399 lines
12 KiB
LLVM
399 lines
12 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -mtriple=riscv32 -target-abi=ilp32d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV32
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; RUN: llc -mtriple=riscv64 -target-abi=lp64d -mattr=+v,+zfh,+experimental-zvfh,+f,+d -riscv-v-vector-bits-min=128 -verify-machineinstrs < %s | FileCheck %s --check-prefixes=CHECK,RV64
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; FIXME: This codegen needs to be improved. These tests previously asserted
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; type legalizing the i64 type on RV32.
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define <4 x i64> @insertelt_v4i64(<4 x i64> %a, i64 %y) {
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; RV32-LABEL: insertelt_v4i64:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 2, e32, m2, ta, ma
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; RV32-NEXT: vslide1down.vx v10, v8, a0
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; RV32-NEXT: vslide1down.vx v10, v10, a1
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: vslideup.vi v8, v10, 3
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v4i64:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vmv.s.x v10, a0
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; RV64-NEXT: vslideup.vi v8, v10, 3
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; RV64-NEXT: ret
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%b = insertelement <4 x i64> %a, i64 %y, i32 3
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ret <4 x i64> %b
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}
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define void @insertelt_v4i64_store(ptr %x, i64 %y) {
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; RV32-LABEL: insertelt_v4i64_store:
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; RV32: # %bb.0:
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; RV32-NEXT: sw a2, 28(a0)
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; RV32-NEXT: sw a1, 24(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v4i64_store:
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; RV64: # %bb.0:
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; RV64-NEXT: sd a1, 24(a0)
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; RV64-NEXT: ret
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%a = load <4 x i64>, ptr %x
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%b = insertelement <4 x i64> %a, i64 %y, i32 3
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store <4 x i64> %b, ptr %x
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ret void
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}
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; This uses a non-power of 2 type so that it isn't an MVT.
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; The align keeps the type legalizer from using a 256 bit load so we must split
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; it. This some operations that weren't support for scalable vectors when
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; this test was written.
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define <3 x i64> @insertelt_v3i64(<3 x i64> %a, i64 %y) {
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; RV32-LABEL: insertelt_v3i64:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 1, e32, m2, ta, ma
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; RV32-NEXT: vslidedown.vi v10, v8, 3
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; RV32-NEXT: vmv.x.s a2, v10
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; RV32-NEXT: vslidedown.vi v10, v8, 2
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; RV32-NEXT: vmv.x.s a3, v10
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; RV32-NEXT: vslidedown.vi v10, v8, 1
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; RV32-NEXT: vmv.x.s a4, v10
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; RV32-NEXT: vmv.x.s a5, v8
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; RV32-NEXT: vsetivli zero, 8, e32, m2, ta, ma
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; RV32-NEXT: vslide1down.vx v8, v8, a5
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; RV32-NEXT: vslide1down.vx v8, v8, a4
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; RV32-NEXT: vslide1down.vx v8, v8, a3
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; RV32-NEXT: vslide1down.vx v8, v8, a2
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; RV32-NEXT: vslide1down.vx v8, v8, a0
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; RV32-NEXT: vslide1down.vx v8, v8, a1
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; RV32-NEXT: vslidedown.vi v8, v8, 2
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v3i64:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 1, e64, m2, ta, ma
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; RV64-NEXT: vslidedown.vi v10, v8, 1
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; RV64-NEXT: vmv.x.s a1, v10
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; RV64-NEXT: vmv.x.s a2, v8
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: vslide1down.vx v8, v8, a2
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; RV64-NEXT: vslide1down.vx v8, v8, a1
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; RV64-NEXT: vslide1down.vx v8, v8, a0
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; RV64-NEXT: vslidedown.vi v8, v8, 1
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; RV64-NEXT: ret
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%b = insertelement <3 x i64> %a, i64 %y, i32 2
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ret <3 x i64> %b
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}
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define void @insertelt_v3i64_store(ptr %x, i64 %y) {
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; RV32-LABEL: insertelt_v3i64_store:
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; RV32: # %bb.0:
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; RV32-NEXT: sw a2, 20(a0)
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; RV32-NEXT: sw a1, 16(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v3i64_store:
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; RV64: # %bb.0:
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; RV64-NEXT: sd a1, 16(a0)
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; RV64-NEXT: ret
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%a = load <3 x i64>, ptr %x, align 8
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%b = insertelement <3 x i64> %a, i64 %y, i32 2
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store <3 x i64> %b, ptr %x
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ret void
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}
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define <16 x i8> @insertelt_v16i8(<16 x i8> %a, i8 %y) {
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; CHECK-LABEL: insertelt_v16i8:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 15, e8, m1, tu, ma
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; CHECK-NEXT: vmv.s.x v9, a0
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; CHECK-NEXT: vslideup.vi v8, v9, 14
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; CHECK-NEXT: ret
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%b = insertelement <16 x i8> %a, i8 %y, i32 14
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ret <16 x i8> %b
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}
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define void @insertelt_v16i8_store(ptr %x, i8 %y) {
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; CHECK-LABEL: insertelt_v16i8_store:
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; CHECK: # %bb.0:
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; CHECK-NEXT: sb a1, 14(a0)
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; CHECK-NEXT: ret
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%a = load <16 x i8>, ptr %x
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%b = insertelement <16 x i8> %a, i8 %y, i32 14
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store <16 x i8> %b, ptr %x
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ret void
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}
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define <32 x i16> @insertelt_v32i16(<32 x i16> %a, i16 %y, i32 %idx) {
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; RV32-LABEL: insertelt_v32i16:
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; RV32: # %bb.0:
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; RV32-NEXT: li a2, 32
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; RV32-NEXT: vsetvli zero, a2, e16, m1, ta, ma
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; RV32-NEXT: vmv.s.x v12, a0
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; RV32-NEXT: addi a0, a1, 1
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; RV32-NEXT: vsetvli zero, a0, e16, m4, tu, ma
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; RV32-NEXT: vslideup.vx v8, v12, a1
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v32i16:
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; RV64: # %bb.0:
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; RV64-NEXT: li a2, 32
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; RV64-NEXT: vsetvli zero, a2, e16, m1, ta, ma
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; RV64-NEXT: vmv.s.x v12, a0
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; RV64-NEXT: slli a1, a1, 32
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; RV64-NEXT: srli a1, a1, 32
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; RV64-NEXT: addi a0, a1, 1
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; RV64-NEXT: vsetvli zero, a0, e16, m4, tu, ma
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; RV64-NEXT: vslideup.vx v8, v12, a1
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; RV64-NEXT: ret
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%b = insertelement <32 x i16> %a, i16 %y, i32 %idx
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ret <32 x i16> %b
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}
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define void @insertelt_v32i16_store(ptr %x, i16 %y, i32 %idx) {
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; RV32-LABEL: insertelt_v32i16_store:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a2, a2, 1
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; RV32-NEXT: add a0, a0, a2
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; RV32-NEXT: sh a1, 0(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v32i16_store:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a2, a2, 32
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; RV64-NEXT: srli a2, a2, 31
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; RV64-NEXT: add a0, a0, a2
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; RV64-NEXT: sh a1, 0(a0)
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; RV64-NEXT: ret
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%a = load <32 x i16>, ptr %x
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%b = insertelement <32 x i16> %a, i16 %y, i32 %idx
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store <32 x i16> %b, ptr %x
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ret void
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}
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define <8 x float> @insertelt_v8f32(<8 x float> %a, float %y, i32 %idx) {
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; RV32-LABEL: insertelt_v8f32:
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; RV32: # %bb.0:
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; RV32-NEXT: vsetivli zero, 8, e32, m1, ta, ma
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; RV32-NEXT: vfmv.s.f v10, fa0
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; RV32-NEXT: addi a1, a0, 1
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; RV32-NEXT: vsetvli zero, a1, e32, m2, tu, ma
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; RV32-NEXT: vslideup.vx v8, v10, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v8f32:
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; RV64: # %bb.0:
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; RV64-NEXT: vsetivli zero, 8, e32, m1, ta, ma
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; RV64-NEXT: vfmv.s.f v10, fa0
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; RV64-NEXT: slli a0, a0, 32
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; RV64-NEXT: srli a0, a0, 32
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; RV64-NEXT: addi a1, a0, 1
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; RV64-NEXT: vsetvli zero, a1, e32, m2, tu, ma
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; RV64-NEXT: vslideup.vx v8, v10, a0
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; RV64-NEXT: ret
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%b = insertelement <8 x float> %a, float %y, i32 %idx
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ret <8 x float> %b
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}
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define void @insertelt_v8f32_store(ptr %x, float %y, i32 %idx) {
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; RV32-LABEL: insertelt_v8f32_store:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a1, a1, 2
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: fsw fa0, 0(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v8f32_store:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a1, a1, 32
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; RV64-NEXT: srli a1, a1, 30
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: fsw fa0, 0(a0)
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; RV64-NEXT: ret
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%a = load <8 x float>, ptr %x
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%b = insertelement <8 x float> %a, float %y, i32 %idx
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store <8 x float> %b, ptr %x
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ret void
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}
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define <8 x i64> @insertelt_v8i64_0(<8 x i64> %a, ptr %x) {
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; CHECK-LABEL: insertelt_v8i64_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vsetivli zero, 8, e64, m4, tu, ma
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; CHECK-NEXT: vmv.s.x v8, a0
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; CHECK-NEXT: ret
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%b = insertelement <8 x i64> %a, i64 -1, i32 0
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ret <8 x i64> %b
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}
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define void @insertelt_v8i64_0_store(ptr %x) {
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; RV32-LABEL: insertelt_v8i64_0_store:
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; RV32: # %bb.0:
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; RV32-NEXT: li a1, -1
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; RV32-NEXT: sw a1, 4(a0)
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; RV32-NEXT: sw a1, 0(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v8i64_0_store:
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; RV64: # %bb.0:
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; RV64-NEXT: li a1, -1
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; RV64-NEXT: sd a1, 0(a0)
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; RV64-NEXT: ret
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%a = load <8 x i64>, ptr %x
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%b = insertelement <8 x i64> %a, i64 -1, i32 0
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store <8 x i64> %b, ptr %x
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ret void
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}
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define <8 x i64> @insertelt_v8i64(<8 x i64> %a, i32 %idx) {
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; RV32-LABEL: insertelt_v8i64:
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; RV32: # %bb.0:
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; RV32-NEXT: li a1, -1
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; RV32-NEXT: vsetivli zero, 8, e64, m1, ta, ma
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; RV32-NEXT: vmv.s.x v12, a1
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; RV32-NEXT: addi a1, a0, 1
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; RV32-NEXT: vsetvli zero, a1, e64, m4, tu, ma
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; RV32-NEXT: vslideup.vx v8, v12, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v8i64:
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; RV64: # %bb.0:
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; RV64-NEXT: li a1, -1
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; RV64-NEXT: vsetivli zero, 8, e64, m1, ta, ma
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; RV64-NEXT: vmv.s.x v12, a1
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; RV64-NEXT: slli a0, a0, 32
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; RV64-NEXT: srli a0, a0, 32
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; RV64-NEXT: addi a1, a0, 1
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; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, ma
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; RV64-NEXT: vslideup.vx v8, v12, a0
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; RV64-NEXT: ret
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%b = insertelement <8 x i64> %a, i64 -1, i32 %idx
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ret <8 x i64> %b
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}
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define void @insertelt_v8i64_store(ptr %x, i32 %idx) {
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; RV32-LABEL: insertelt_v8i64_store:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a1, a1, 3
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: li a1, -1
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; RV32-NEXT: sw a1, 4(a0)
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; RV32-NEXT: sw a1, 0(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_v8i64_store:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a1, a1, 32
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; RV64-NEXT: srli a1, a1, 29
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; RV64-NEXT: add a0, a0, a1
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; RV64-NEXT: li a1, -1
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; RV64-NEXT: sd a1, 0(a0)
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; RV64-NEXT: ret
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%a = load <8 x i64>, ptr %x
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%b = insertelement <8 x i64> %a, i64 -1, i32 %idx
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store <8 x i64> %b, ptr %x
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ret void
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}
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define <8 x i64> @insertelt_c6_v8i64_0(<8 x i64> %a, ptr %x) {
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; CHECK-LABEL: insertelt_c6_v8i64_0:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 6
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; CHECK-NEXT: vsetivli zero, 8, e64, m4, tu, ma
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; CHECK-NEXT: vmv.s.x v8, a0
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; CHECK-NEXT: ret
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%b = insertelement <8 x i64> %a, i64 6, i32 0
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ret <8 x i64> %b
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}
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define void @insertelt_c6_v8i64_0_store(ptr %x) {
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; RV32-LABEL: insertelt_c6_v8i64_0_store:
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; RV32: # %bb.0:
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; RV32-NEXT: sw zero, 4(a0)
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; RV32-NEXT: li a1, 6
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; RV32-NEXT: sw a1, 0(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_c6_v8i64_0_store:
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; RV64: # %bb.0:
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; RV64-NEXT: li a1, 6
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; RV64-NEXT: sd a1, 0(a0)
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; RV64-NEXT: ret
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%a = load <8 x i64>, ptr %x
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%b = insertelement <8 x i64> %a, i64 6, i32 0
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store <8 x i64> %b, ptr %x
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ret void
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}
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define <8 x i64> @insertelt_c6_v8i64(<8 x i64> %a, i32 %idx) {
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; RV32-LABEL: insertelt_c6_v8i64:
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; RV32: # %bb.0:
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; RV32-NEXT: li a1, 6
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; RV32-NEXT: vsetivli zero, 8, e64, m1, ta, ma
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; RV32-NEXT: vmv.s.x v12, a1
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; RV32-NEXT: addi a1, a0, 1
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; RV32-NEXT: vsetvli zero, a1, e64, m4, tu, ma
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; RV32-NEXT: vslideup.vx v8, v12, a0
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_c6_v8i64:
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; RV64: # %bb.0:
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; RV64-NEXT: li a1, 6
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; RV64-NEXT: vsetivli zero, 8, e64, m1, ta, ma
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; RV64-NEXT: vmv.s.x v12, a1
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; RV64-NEXT: slli a0, a0, 32
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; RV64-NEXT: srli a0, a0, 32
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; RV64-NEXT: addi a1, a0, 1
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; RV64-NEXT: vsetvli zero, a1, e64, m4, tu, ma
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; RV64-NEXT: vslideup.vx v8, v12, a0
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; RV64-NEXT: ret
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%b = insertelement <8 x i64> %a, i64 6, i32 %idx
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ret <8 x i64> %b
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}
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define void @insertelt_c6_v8i64_store(ptr %x, i32 %idx) {
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; RV32-LABEL: insertelt_c6_v8i64_store:
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; RV32: # %bb.0:
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; RV32-NEXT: slli a1, a1, 3
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; RV32-NEXT: add a0, a0, a1
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; RV32-NEXT: sw zero, 4(a0)
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; RV32-NEXT: li a1, 6
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; RV32-NEXT: sw a1, 0(a0)
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; RV32-NEXT: ret
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;
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; RV64-LABEL: insertelt_c6_v8i64_store:
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; RV64: # %bb.0:
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; RV64-NEXT: slli a1, a1, 32
|
|
; RV64-NEXT: srli a1, a1, 29
|
|
; RV64-NEXT: add a0, a0, a1
|
|
; RV64-NEXT: li a1, 6
|
|
; RV64-NEXT: sd a1, 0(a0)
|
|
; RV64-NEXT: ret
|
|
%a = load <8 x i64>, ptr %x
|
|
%b = insertelement <8 x i64> %a, i64 6, i32 %idx
|
|
store <8 x i64> %b, ptr %x
|
|
ret void
|
|
}
|
|
|
|
; Test that using a insertelement at element 0 by a later operation doesn't
|
|
; crash the compiler.
|
|
define void @insertelt_c6_v8i64_0_add(ptr %x, ptr %y) {
|
|
; CHECK-LABEL: insertelt_c6_v8i64_0_add:
|
|
; CHECK: # %bb.0:
|
|
; CHECK-NEXT: vsetivli zero, 8, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle64.v v8, (a0)
|
|
; CHECK-NEXT: li a2, 6
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m4, tu, ma
|
|
; CHECK-NEXT: vmv.s.x v8, a2
|
|
; CHECK-NEXT: vsetvli zero, zero, e64, m4, ta, ma
|
|
; CHECK-NEXT: vle64.v v12, (a1)
|
|
; CHECK-NEXT: vadd.vv v8, v8, v12
|
|
; CHECK-NEXT: vse64.v v8, (a0)
|
|
; CHECK-NEXT: ret
|
|
%a = load <8 x i64>, ptr %x
|
|
%b = insertelement <8 x i64> %a, i64 6, i32 0
|
|
%c = load <8 x i64>, ptr %y
|
|
%d = add <8 x i64> %b, %c
|
|
store <8 x i64> %d, ptr %x
|
|
ret void
|
|
}
|