92b5a3405d
This change continues with the line of work discussed in https://discourse.llvm.org/t/riscv-transition-in-vector-pseudo-structure-policy-variants/71295. In D153155, we started removing the legacy distinction between unsuffixed (TA) and _TU pseudos. This patch continues that effort for the unary instruction families. The change consists of a few interacting pieces: * Adding a vector policy operand to VPseudoUnaryNoMaskTU. * Then using VPseudoUnaryNoMaskTU for all cases where VPseudoUnaryNoMask was previously used and deleting the unsuffixed form. * Then renaming VPseudoUnaryNoMaskTU to VPseudoUnaryNoMask, and adjusting the RISCVMaskedPseudo table to use the combined pseudo. * Fixing up two places in C++ code which manually construct VMV_V_* instructions. Normally, I'd try to factor this into a couple of changes, but in this case, the table structure is tied to naming and thus we can't really separate the otherwise NFC bits. As before, we see codegen changes (some improvements and some regressions) due to scheduling differences caused by the extra implicit_def instructions. Differential Revision: https://reviews.llvm.org/D153899
191 lines
7.4 KiB
LLVM
191 lines
7.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc < %s -mtriple=riscv32 -mattr=+v,+zfh,+experimental-zvfh | FileCheck -check-prefixes=CHECK,RV32 %s
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; RUN: llc < %s -mtriple=riscv64 -mattr=+v,+zfh,+experimental-zvfh | FileCheck -check-prefixes=CHECK,RV64 %s
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; Integers
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define <32 x i1> @vector_interleave_v32i1_v16i1(<16 x i1> %a, <16 x i1> %b) {
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; CHECK-LABEL: vector_interleave_v32i1_v16i1:
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; CHECK: # %bb.0:
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; CHECK-NEXT: li a0, 32
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; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
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; CHECK-NEXT: vmv.v.i v10, 0
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; CHECK-NEXT: vsetivli zero, 4, e8, mf4, ta, ma
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; CHECK-NEXT: vslideup.vi v0, v8, 2
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; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
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; CHECK-NEXT: vmerge.vim v8, v10, 1, v0
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; CHECK-NEXT: vsetivli zero, 16, e8, m2, ta, ma
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; CHECK-NEXT: vslidedown.vi v10, v8, 16
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; CHECK-NEXT: vsetivli zero, 16, e8, m1, ta, ma
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; CHECK-NEXT: vwaddu.vv v12, v8, v10
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; CHECK-NEXT: li a1, -1
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; CHECK-NEXT: vwmaccu.vx v12, a1, v10
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; CHECK-NEXT: vsetvli zero, a0, e8, m2, ta, ma
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; CHECK-NEXT: vmsne.vi v0, v12, 0
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; CHECK-NEXT: ret
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%res = call <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1> %a, <16 x i1> %b)
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ret <32 x i1> %res
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}
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define <16 x i16> @vector_interleave_v16i16_v8i16(<8 x i16> %a, <8 x i16> %b) {
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; CHECK-LABEL: vector_interleave_v16i16_v8i16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vwaddu.vv v10, v8, v9
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v10, a0, v9
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; CHECK-NEXT: vmv2r.v v8, v10
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; CHECK-NEXT: ret
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%res = call <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16> %a, <8 x i16> %b)
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ret <16 x i16> %res
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}
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define <8 x i32> @vector_interleave_v8i32_v4i32(<4 x i32> %a, <4 x i32> %b) {
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; CHECK-LABEL: vector_interleave_v8i32_v4i32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vwaddu.vv v10, v8, v9
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v10, a0, v9
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; CHECK-NEXT: vmv2r.v v8, v10
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; CHECK-NEXT: ret
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%res = call <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32> %a, <4 x i32> %b)
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ret <8 x i32> %res
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}
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define <4 x i64> @vector_interleave_v4i64_v2i64(<2 x i64> %a, <2 x i64> %b) {
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; RV32-LABEL: vector_interleave_v4i64_v2i64:
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; RV32: # %bb.0:
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; RV32-NEXT: vmv1r.v v10, v9
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: lui a0, %hi(.LCPI3_0)
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; RV32-NEXT: addi a0, a0, %lo(.LCPI3_0)
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; RV32-NEXT: vle16.v v12, (a0)
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; RV32-NEXT: vslideup.vi v8, v10, 2
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; RV32-NEXT: vrgatherei16.vv v10, v8, v12
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; RV32-NEXT: vmv.v.v v8, v10
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; RV32-NEXT: ret
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;
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; RV64-LABEL: vector_interleave_v4i64_v2i64:
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; RV64: # %bb.0:
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; RV64-NEXT: vmv1r.v v10, v9
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: lui a0, %hi(.LCPI3_0)
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; RV64-NEXT: addi a0, a0, %lo(.LCPI3_0)
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; RV64-NEXT: vle64.v v12, (a0)
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; RV64-NEXT: vslideup.vi v8, v10, 2
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; RV64-NEXT: vrgather.vv v10, v8, v12
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; RV64-NEXT: vmv.v.v v8, v10
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; RV64-NEXT: ret
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%res = call <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64> %a, <2 x i64> %b)
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ret <4 x i64> %res
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}
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declare <32 x i1> @llvm.experimental.vector.interleave2.v32i1(<16 x i1>, <16 x i1>)
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declare <16 x i16> @llvm.experimental.vector.interleave2.v16i16(<8 x i16>, <8 x i16>)
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declare <8 x i32> @llvm.experimental.vector.interleave2.v8i32(<4 x i32>, <4 x i32>)
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declare <4 x i64> @llvm.experimental.vector.interleave2.v4i64(<2 x i64>, <2 x i64>)
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; Floats
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define <4 x half> @vector_interleave_v4f16_v2f16(<2 x half> %a, <2 x half> %b) {
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; CHECK-LABEL: vector_interleave_v4f16_v2f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e16, mf4, ta, ma
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; CHECK-NEXT: vwaddu.vv v10, v8, v9
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v10, a0, v9
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; CHECK-NEXT: vmv1r.v v8, v10
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; CHECK-NEXT: ret
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%res = call <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half> %a, <2 x half> %b)
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ret <4 x half> %res
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}
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define <8 x half> @vector_interleave_v8f16_v4f16(<4 x half> %a, <4 x half> %b) {
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; CHECK-LABEL: vector_interleave_v8f16_v4f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e16, mf2, ta, ma
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; CHECK-NEXT: vwaddu.vv v10, v8, v9
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v10, a0, v9
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; CHECK-NEXT: vmv1r.v v8, v10
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; CHECK-NEXT: ret
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%res = call <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half> %a, <4 x half> %b)
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ret <8 x half> %res
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}
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define <4 x float> @vector_interleave_v4f32_v2f32(<2 x float> %a, <2 x float> %b) {
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; CHECK-LABEL: vector_interleave_v4f32_v2f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 2, e32, mf2, ta, ma
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; CHECK-NEXT: vwaddu.vv v10, v8, v9
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v10, a0, v9
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; CHECK-NEXT: vmv1r.v v8, v10
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; CHECK-NEXT: ret
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%res = call <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float> %a, <2 x float> %b)
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ret <4 x float> %res
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}
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define <16 x half> @vector_interleave_v16f16_v8f16(<8 x half> %a, <8 x half> %b) {
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; CHECK-LABEL: vector_interleave_v16f16_v8f16:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 8, e16, m1, ta, ma
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; CHECK-NEXT: vwaddu.vv v10, v8, v9
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v10, a0, v9
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; CHECK-NEXT: vmv2r.v v8, v10
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; CHECK-NEXT: ret
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%res = call <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half> %a, <8 x half> %b)
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ret <16 x half> %res
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}
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define <8 x float> @vector_interleave_v8f32_v4f32(<4 x float> %a, <4 x float> %b) {
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; CHECK-LABEL: vector_interleave_v8f32_v4f32:
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; CHECK: # %bb.0:
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; CHECK-NEXT: vsetivli zero, 4, e32, m1, ta, ma
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; CHECK-NEXT: vwaddu.vv v10, v8, v9
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; CHECK-NEXT: li a0, -1
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; CHECK-NEXT: vwmaccu.vx v10, a0, v9
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; CHECK-NEXT: vmv2r.v v8, v10
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; CHECK-NEXT: ret
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%res = call <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float> %a, <4 x float> %b)
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ret <8 x float> %res
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}
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define <4 x double> @vector_interleave_v4f64_v2f64(<2 x double> %a, <2 x double> %b) {
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; RV32-LABEL: vector_interleave_v4f64_v2f64:
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; RV32: # %bb.0:
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; RV32-NEXT: vmv1r.v v10, v9
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; RV32-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV32-NEXT: lui a0, %hi(.LCPI9_0)
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; RV32-NEXT: addi a0, a0, %lo(.LCPI9_0)
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; RV32-NEXT: vle16.v v12, (a0)
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; RV32-NEXT: vslideup.vi v8, v10, 2
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; RV32-NEXT: vrgatherei16.vv v10, v8, v12
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; RV32-NEXT: vmv.v.v v8, v10
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; RV32-NEXT: ret
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;
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; RV64-LABEL: vector_interleave_v4f64_v2f64:
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; RV64: # %bb.0:
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; RV64-NEXT: vmv1r.v v10, v9
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; RV64-NEXT: vsetivli zero, 4, e64, m2, ta, ma
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; RV64-NEXT: lui a0, %hi(.LCPI9_0)
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; RV64-NEXT: addi a0, a0, %lo(.LCPI9_0)
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; RV64-NEXT: vle64.v v12, (a0)
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; RV64-NEXT: vslideup.vi v8, v10, 2
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; RV64-NEXT: vrgather.vv v10, v8, v12
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; RV64-NEXT: vmv.v.v v8, v10
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; RV64-NEXT: ret
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%res = call <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double> %a, <2 x double> %b)
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ret <4 x double> %res
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}
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declare <4 x half> @llvm.experimental.vector.interleave2.v4f16(<2 x half>, <2 x half>)
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declare <8 x half> @llvm.experimental.vector.interleave2.v8f16(<4 x half>, <4 x half>)
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declare <4 x float> @llvm.experimental.vector.interleave2.v4f32(<2 x float>, <2 x float>)
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declare <16 x half> @llvm.experimental.vector.interleave2.v16f16(<8 x half>, <8 x half>)
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declare <8 x float> @llvm.experimental.vector.interleave2.v8f32(<4 x float>, <4 x float>)
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declare <4 x double> @llvm.experimental.vector.interleave2.v4f64(<2 x double>, <2 x double>)
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