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llvm-project/llvm/test/Transforms/LoopVectorize/RISCV
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Luke Lau b9af086292 [RISCV] Update loop vectorizer interleaved access test output 
02bb33c3ce7a83d47244ae16c8b4c625aba187a2 changed it so it no longer unrolls the
loop.
2023-07-07 15:38:04 +01:00
..
defaults.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
divrem.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
force-vect-msg.ll
[NFC] Port all runlines for LoopVectorize pass tests to -passes syntax
2022-12-05 22:17:30 +03:00
illegal-type.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
inloop-reduction.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
interleaved-accesses-zve32x.ll
[RISCV][NFC] Add tests for interleaved accesses in loop vectorizer
2023-03-09 17:43:16 +00:00
interleaved-accesses.ll
[RISCV] Update loop vectorizer interleaved access test output
2023-07-07 15:38:04 +01:00
interleaved-cost.ll
[RISCV] Account for LMUL in memory op costs
2023-04-05 07:58:56 -07:00
lit.local.cfg
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
lmul.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
low-trip-count.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
mask-index-type.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
masked_gather_scatter.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
ordered-reduction.ll
[RISCV] Enable ordered reduction.
2023-03-07 04:36:50 -08:00
reg-usage.ll
[LV] Reland "Update logic for calculating register usage due to invariants"
2023-02-28 17:32:39 +05:30
riscv-interleaved.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
riscv-unroll.ll
[LV] Optimize trip count SCEV.
2023-04-12 16:17:58 -07:00
riscv-vector-reverse.ll
[VPlan] Print IR flags for VPRecipeWithIRFlags.
2023-05-23 20:36:16 +01:00
safe-dep-distance.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
scalable-basics.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
scalable-reductions.ll
[IR] llvm::createMinMaxOp - create integer min/max intrinsics instead of icmp/sel
2023-04-13 16:40:43 +01:00
scalable-tailfold.ll
[NFC][LoopVectorize] Change trip counts for some tests to guarantee a scalar tail
2023-03-24 09:43:50 +00:00
scalable-vf-hint.ll
[LoopVectorize] Convert some tests to opaque pointers (NFC)
2022-12-14 15:16:59 +01:00
select-cmp-reduction.ll
[LoopVectorize] Convert most tests to opaque pointers (NFC)
2023-06-12 13:10:22 +02:00
short-trip-count.ll
[RISCV] Increase default vectorizer LMUL to 2
2023-03-23 10:33:50 +00:00
strided-accesses.ll
[VPlan] Replace versioned stride with constant during VPlan opts.
2023-06-13 08:26:55 +01:00
uniform-load-store.ll
[NFC][LoopVectorize] Change trip counts for some tests to guarantee a scalar tail
2023-03-24 09:43:50 +00:00
unroll-in-loop-vectorizer.ll
[LoopVectorize] Convert some tests to opaque pointers (NFC)
2022-12-14 15:16:59 +01:00
zvl32b.ll
[RISCV] Account for LMUL in memory op costs
2023-04-05 07:58:56 -07:00