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llvm-project/llvm/test/Transforms/PhaseOrdering/AArch64
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Zhongyunde cb353dc74e [LV] Add cost model for simd vector select instructions of type float
For simd vector selects, use cmeq + bsl for v2f32/v4f32/v2f64, so their cost are cheep.
Fix https://github.com/llvm/llvm-project/issues/63082

Reviewed By: dmgreen
Differential Revision: https://reviews.llvm.org/D152523
2023-06-20 13:12:19 +08:00
..
globals-aa-required-for-vectorization.ll
…
hoisting-sinking-required-for-vectorization.ll
[LV] Add cost model for simd vector select instructions of type float
2023-06-20 13:12:19 +08:00
lit.local.cfg
[NFC][Py Reformat] Reformat lit.local.cfg python files in llvm
2023-05-17 17:03:15 +02:00
loopflatten.ll
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matrix-extract-insert.ll
[PhaseOrdering] Regenerate test checks (NFC)
2023-06-14 10:08:46 +02:00
mul-ov.ll
…
peel-multiple-unreachable-exits-for-vectorization.ll
…
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