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llvm-project/llvm/lib/Target/AMDGPU
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Matt Arsenault d6fdbbcace AMDGPU: Add second emergency slot for SGPR to vmem for large frames 
In a future change, we will sometimes use a VGPR offset for doing
spills to memory, in which case we need 2 free VGPRs to do the SGPR
spill. In most cases we could spill the VGPR along with the SGPR being
spilled, but we don't have any free lanes for SGPR_1024 in wave32 so
we could still potentially need a second scavenging slot.
2022-02-02 19:05:05 -05:00
..
AsmParser
[AMDGPU][NFC] Fixing formatting
2022-02-01 17:59:01 -08:00
Disassembler
[AMDGPU] Support shared literals in FMAMK/FMAAK
2021-10-11 13:09:54 -04:00
MCA
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
MCTargetDesc
AMDGPU {NFC}: Add code object v5 support and generate metadata for implicit kernel args
2022-01-31 18:07:47 -08:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
Utils
AMDGPU {NFC}: Add code object v5 support and generate metadata for implicit kernel args
2022-01-31 18:07:47 -08:00
AMDGPU.h
Cleanup header dependencies in LLVMCore
2022-02-02 06:54:20 +01:00
AMDGPU.td
[AMDGPU] Remove feature register-banking
2022-01-26 08:39:17 -08:00
AMDGPUAliasAnalysis.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
AMDGPUAliasAnalysis.h
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
AMDGPUAlwaysInlinePass.cpp
[HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate undefined symbols
2021-10-18 16:53:15 -06:00
AMDGPUAnnotateKernelFeatures.cpp
…
AMDGPUAnnotateUniformValues.cpp
[AMDGPU] Use new target MMO flag MONoClobber
2022-02-02 17:12:36 +00:00
AMDGPUArgumentUsageInfo.cpp
AMDGPU: Remove fixed function ABI option
2021-12-10 19:41:19 -05:00
AMDGPUArgumentUsageInfo.h
…
AMDGPUAsmPrinter.cpp
AMDGPU {NFC}: Add code object v5 support and generate metadata for implicit kernel args
2022-01-31 18:07:47 -08:00
AMDGPUAsmPrinter.h
[AMDGPU] Remove unused declaration findNumUsedRegistersSI (NFC)
2021-10-27 21:24:02 -07:00
AMDGPUAtomicOptimizer.cpp
…
AMDGPUAttributor.cpp
AMDGPU: Return result from indicatePessimisticFixpoint
2021-12-16 11:26:30 -05:00
AMDGPUCallingConv.td
Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range"
2021-12-22 11:39:28 -05:00
AMDGPUCallLowering.cpp
AMDGPU/GlobalISel: Fix flat_scratch_init handling for shaders
2022-01-27 10:20:52 -05:00
AMDGPUCallLowering.h
…
AMDGPUCodeGenPrepare.cpp
[ValueTracking][SelectionDAG] Rename ComputeMinSignedBits->ComputeMaxSignificantBits. NFC
2022-01-03 11:33:30 -08:00
AMDGPUCombine.td
AMDGPU/GlobalISel: Add clamp combine
2021-12-03 12:49:39 +01:00
AMDGPUCombinerHelper.cpp
Remove redundant return and continue statements (NFC)
2021-12-24 23:17:54 -08:00
AMDGPUCombinerHelper.h
[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods
2021-11-17 14:25:13 +01:00
AMDGPUCtorDtorLowering.cpp
[amdgpu] Don't crash on empty global ctor/dtor
2021-11-16 14:36:08 +00:00
AMDGPUExportClustering.cpp
…
AMDGPUExportClustering.h
…
AMDGPUFeatures.td
…
AMDGPUFixFunctionBitcasts.cpp
Revert "AMDGPU: Remove AMDGPUFixFunctionBitcasts pass"
2021-12-16 21:21:32 +00:00
AMDGPUFrameLowering.cpp
…
AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
…
AMDGPUGISel.td
AMDGPU/GlobalISel: Add clamp combine
2021-12-03 12:49:39 +01:00
AMDGPUGlobalISelUtils.cpp
…
AMDGPUGlobalISelUtils.h
…
AMDGPUHSAMetadataStreamer.cpp
AMDGPU {NFC}: Add code object v5 support and generate metadata for implicit kernel args
2022-01-31 18:07:47 -08:00
AMDGPUHSAMetadataStreamer.h
AMDGPU {NFC}: Add code object v5 support and generate metadata for implicit kernel args
2022-01-31 18:07:47 -08:00
AMDGPUInstCombineIntrinsic.cpp
[AMDGPU] Only match correct type for a16
2022-01-25 14:59:16 +01:00
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
[AMDGPU] Fix LOD bias in A16 combine
2022-01-21 12:09:06 +01:00
AMDGPUInstrInfo.td
Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range"
2021-12-22 11:39:28 -05:00
AMDGPUInstructions.td
[AMDGPU] Set MemoryVT for truncstores in tblgen.
2022-01-20 19:05:12 +05:30
AMDGPUInstructionSelector.cpp
AMDGPU/GlobalISel: Fix assert on invalid cond code for llvm.amdgcn.icmp
2022-01-27 10:34:06 -05:00
AMDGPUInstructionSelector.h
AMDGPU/GlobalISel: Introduce pseudo to copy sp in call sequences
2022-01-19 10:13:31 -05:00
AMDGPUISelDAGToDAG.cpp
[AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32
2021-11-24 11:25:02 +00:00
AMDGPUISelDAGToDAG.h
[AMDGPU] Implement widening multiplies with v_mad_i64_i32/v_mad_u64_u32
2021-11-24 11:25:02 +00:00
AMDGPUISelLowering.cpp
[AMDGPU] Make v8i16/v8f16 legal
2022-01-24 11:51:08 -08:00
AMDGPUISelLowering.h
[GlobalISel] Fix typo Extact to Extract in function name. NFC.
2022-01-07 11:13:35 +00:00
AMDGPULateCodeGenPrepare.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
AMDGPULegalizerInfo.cpp
AMDGPU {NFC}: Add code object v5 support and generate metadata for implicit kernel args
2022-01-31 18:07:47 -08:00
AMDGPULegalizerInfo.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AMDGPULibCalls.cpp
Cleanup header dependencies in LLVMCore
2022-02-02 06:54:20 +01:00
AMDGPULibFunc.cpp
Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C++17"
2022-01-26 16:55:53 +01:00
AMDGPULibFunc.h
Move STLFunctionalExtras out of STLExtras
2022-01-24 14:13:21 +01:00
AMDGPULowerIntrinsics.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
AMDGPULowerKernelArguments.cpp
…
AMDGPULowerKernelAttributes.cpp
…
AMDGPULowerModuleLDSPass.cpp
[amdgpu] Increase alignment of all LDS variables
2021-12-12 19:30:32 +00:00
AMDGPUMachineCFGStructurizer.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
AMDGPUMachineFunction.cpp
[Target] Remove redundant member initialization (NFC)
2022-01-06 22:01:44 -08:00
AMDGPUMachineFunction.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AMDGPUMachineModuleInfo.cpp
…
AMDGPUMachineModuleInfo.h
…
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
…
AMDGPUMCInstLower.cpp
Revert "[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range"
2021-12-22 11:39:28 -05:00
AMDGPUMCInstLower.h
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
AMDGPUMIRFormatter.cpp
…
AMDGPUMIRFormatter.h
…
AMDGPUOpenCLEnqueuedBlockLowering.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
AMDGPUPerfHintAnalysis.cpp
[AMDGPUPerfHintAnalysis] Avoid getPointerElementType()
2021-12-13 16:48:21 +01:00
AMDGPUPerfHintAnalysis.h
…
AMDGPUPostLegalizerCombiner.cpp
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
AMDGPUPreLegalizerCombiner.cpp
[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods
2021-11-17 14:25:13 +01:00
AMDGPUPrintfRuntimeBinding.cpp
[llvm] Use nullptr instead of 0 (NFC)
2021-12-28 08:52:25 -08:00
AMDGPUPromoteAlloca.cpp
Cleanup header dependencies in LLVMCore
2022-02-02 06:54:20 +01:00
AMDGPUPromoteKernelArguments.cpp
[AMDGPU] Promote generic pointer kernel arguments into global
2021-10-12 10:07:33 -07:00
AMDGPUPropagateAttributes.cpp
AMDGPU: Use attributor to propagate amdgpu-flat-work-group-size
2021-10-22 16:23:50 -04:00
AMDGPUPTNote.h
[NFC] Fix endif comments to match with include guard
2022-01-07 15:52:59 +08:00
AMDGPURegBankCombiner.cpp
AMDGPU/GlobalISel: Fix introducing f16 fmed3 for gfx8
2022-01-19 10:43:21 -05:00
AMDGPURegisterBankInfo.cpp
[AMDGPU] Use new target MMO flag MONoClobber
2022-02-02 17:12:36 +00:00
AMDGPURegisterBankInfo.h
[AMDGPU] Remove selectStoreIntrinsic (NFC)
2021-11-14 19:40:44 -08:00
AMDGPURegisterBanks.td
…
AMDGPUReplaceLDSUseWithPointer.cpp
[llvm] Use depth_first (NFC)
2021-12-21 22:28:48 -08:00
AMDGPUResourceUsageAnalysis.cpp
AMDGPU: Report large stack usage for recursive calls
2021-11-10 20:02:01 -05:00
AMDGPUResourceUsageAnalysis.h
[AMDGPU] Set number vgprs used in PS shaders based on input registers actually used
2021-10-08 14:24:35 +01:00
AMDGPURewriteOutArguments.cpp
[NFC] Remove uses of PointerType::getElementType()
2022-01-25 09:44:52 +01:00
AMDGPUSearchableTables.td
…
AMDGPUSubtarget.cpp
[AMDGPU] Remove feature register-banking
2022-01-26 08:39:17 -08:00
AMDGPUSubtarget.h
AMDGPU: Stop reserving 36-bytes before kernel arguments for amdpal
2022-01-20 12:12:05 -05:00
AMDGPUTargetMachine.cpp
Revert "AMDGPU: Remove AMDGPUFixFunctionBitcasts pass"
2021-12-16 21:21:32 +00:00
AMDGPUTargetMachine.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
[AMDGPU] Fixed physreg asm constraint parsing
2022-01-12 16:37:08 -08:00
AMDGPUTargetTransformInfo.h
…
AMDGPUUnifyDivergentExitNodes.cpp
…
AMDGPUUnifyMetadata.cpp
…
AMDILCFGStructurizer.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 22:34:07 -08:00
AMDKernelCodeT.h
…
BUFInstructions.td
[AMDGPU][NFC] Alter ComplexPattern types to be consistent with their uses
2021-12-03 07:04:59 +00:00
CaymanInstructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
CMakeLists.txt
Revert "AMDGPU: Remove AMDGPUFixFunctionBitcasts pass"
2021-12-16 21:21:32 +00:00
DSInstructions.td
[AMDGPU] Test commit. NFC.
2022-01-04 23:18:13 -05:00
EvergreenInstructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
EXPInstructions.td
…
FLATInstructions.td
AMDGPU/GlobalISel: Fix selection of gfx90a FP atomics
2022-01-20 12:12:06 -05:00
GCNDPPCombine.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
GCNHazardRecognizer.cpp
[AMDGPU] Prevent aliasing of SrcC and Dst in MAI
2022-01-26 14:48:20 -08:00
GCNHazardRecognizer.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
GCNILPSched.cpp
…
GCNIterativeScheduler.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNIterativeScheduler.h
…
GCNMinRegStrategy.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNNSAReassign.cpp
…
GCNPreRAOptimizations.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNProcessors.td
…
GCNRegPressure.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
GCNRegPressure.h
…
GCNSchedStrategy.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNSchedStrategy.h
[NFC] Fix endif comments to match with include guard
2022-01-07 15:52:59 +08:00
GCNSubtarget.h
[AMDGPU] Remove feature register-banking
2022-01-26 08:39:17 -08:00
InstCombineTables.td
…
MIMGInstructions.td
[AMDGPU][InstCombine] Remove zero image offset
2022-01-24 18:06:33 +01:00
R600.h
…
R600.td
…
R600AsmPrinter.cpp
…
R600AsmPrinter.h
…
R600ClauseMergePass.cpp
[Target] Use range-based for loops (NFC)
2021-11-22 08:21:07 -08:00
R600ControlFlowFinalizer.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 22:34:07 -08:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
[Target] Use range-based for loops (NFC)
2021-11-22 08:21:07 -08:00
R600ExpandSpecialInstrs.cpp
[Target] Use range-based for loops (NFC)
2021-11-22 08:21:07 -08:00
R600FrameLowering.cpp
…
R600FrameLowering.h
…
R600InstrFormats.td
…
R600InstrInfo.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 22:34:07 -08:00
R600InstrInfo.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
R600InstrInfo.td
…
R600Instructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
R600ISelDAGToDAG.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
R600ISelLowering.cpp
[Target] Use range-based for loops (NFC)
2021-11-26 21:21:17 -08:00
R600ISelLowering.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
R600MachineScheduler.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
R600MCInstLower.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
R600OpenCLImageTypeLoweringPass.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
R600OptimizeVectorRegisters.cpp
[Target] Use range-based for loops (NFC)
2021-12-17 10:11:08 -08:00
R600Packetizer.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 22:34:07 -08:00
R600Processors.td
…
R600RegisterInfo.cpp
Revert "Rename llvm::array_lengthof into llvm::size to match std::size from C++17"
2022-01-26 16:55:53 +01:00
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600Subtarget.cpp
…
R600Subtarget.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
R600TargetMachine.cpp
Remove the verifyAfter mechanism that was replaced by D111397
2021-10-18 10:26:46 +01:00
R600TargetMachine.h
…
R600TargetTransformInfo.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
R600TargetTransformInfo.h
…
R700Instructions.td
…
SIAnnotateControlFlow.cpp
AMDGPU: Fix assert on function argument as loop condition
2022-01-12 19:44:26 -05:00
SIDefines.h
[AMDGPU][GFX10][MC] Updated symbolic names of internal HW registers
2022-01-17 20:29:10 +03:00
SIFixSGPRCopies.cpp
[Target] Use range-based for loops (NFC)
2021-11-26 21:21:17 -08:00
SIFixVGPRCopies.cpp
…
SIFoldOperands.cpp
[AMDGPU] Prevent aliasing of SrcC and Dst in MAI
2022-01-26 14:48:20 -08:00
SIFormMemoryClauses.cpp
…
SIFrameLowering.cpp
AMDGPU: Add second emergency slot for SGPR to vmem for large frames
2022-02-02 19:05:05 -05:00
SIFrameLowering.h
[Target] Remove unused forward declarations (NFC)
2022-01-02 10:20:15 -08:00
SIInsertHardClauses.cpp
…
SIInsertWaitcnts.cpp
[AMDGPU][NFC] Fix debug prints
2022-01-24 13:55:00 +01:00
SIInstrFormats.td
…
SIInstrInfo.cpp
[AMDGPU] Use new target MMO flag MONoClobber
2022-02-02 17:12:36 +00:00
SIInstrInfo.h
[AMDGPU] Use new target MMO flag MONoClobber
2022-02-02 17:12:36 +00:00
SIInstrInfo.td
[AMDGPU] Prevent aliasing of SrcC and Dst in MAI
2022-01-26 14:48:20 -08:00
SIInstructions.td
AMDGPU/GlobalISel: Mostly fix BFI patterns
2022-01-26 15:06:50 -05:00
SIISelLowering.cpp
[AMDGPU] Use new target MMO flag MONoClobber
2022-02-02 17:12:36 +00:00
SIISelLowering.h
[AMDGPU] Use new target MMO flag MONoClobber
2022-02-02 17:12:36 +00:00
SILateBranchLowering.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
SILoadStoreOptimizer.cpp
[AMDGPU] SILoadStoreOptimizer: break lists on instructions with side effects
2022-01-28 18:03:42 +00:00
SILowerControlFlow.cpp
[AMDGPU] Disable optimizeEndCf at -O0
2022-01-18 02:48:52 -05:00
SILowerI1Copies.cpp
…
SILowerSGPRSpills.cpp
AMDGPU: Add second emergency slot for SGPR to vmem for large frames
2022-02-02 19:05:05 -05:00
SIMachineFunctionInfo.cpp
AMDGPU: Add second emergency slot for SGPR to vmem for large frames
2022-02-02 19:05:05 -05:00
SIMachineFunctionInfo.h
AMDGPU: Add second emergency slot for SGPR to vmem for large frames
2022-02-02 19:05:05 -05:00
SIMachineScheduler.cpp
[Target] Use range-based for loops (NFC)
2021-12-17 10:11:08 -08:00
SIMachineScheduler.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
SIMemoryLegalizer.cpp
[AMDGPU] Add SIMemoryLegalizer comments to clarify bit usage
2021-11-26 21:05:58 +09:00
SIModeRegister.cpp
[llvm] Use nullptr instead of 0 (NFC)
2021-12-28 08:52:25 -08:00
SIOptimizeExecMasking.cpp
…
SIOptimizeExecMaskingPreRA.cpp
…
SIOptimizeVGPRLiveRange.cpp
AMDGPU: Fix LiveVariables error after optimizing VGPR ranges
2022-01-17 09:38:35 -05:00
SIPeepholeSDWA.cpp
[AMDGPU] Add a regclass flag for scalar registers
2021-12-01 23:31:07 -05:00
SIPostRABundler.cpp
[AMDGPU] Fix SIPostRABundler crash on null register used by dbg value
2021-11-18 17:01:19 -08:00
SIPreAllocateWWMRegs.cpp
…
SIPreEmitPeephole.cpp
[Target] Use range-based for loops (NFC)
2021-11-22 08:21:07 -08:00
SIProgramInfo.cpp
…
SIProgramInfo.h
…
SIRegisterInfo.cpp
AMDGPU: Implement isAsmClobberable
2022-02-02 14:20:12 -05:00
SIRegisterInfo.h
AMDGPU: Implement isAsmClobberable
2022-02-02 14:20:12 -05:00
SIRegisterInfo.td
[AMDGPU] Make v8i16/v8f16 legal
2022-01-24 11:51:08 -08:00
SISchedule.td
[AMDGPU] Set most sched model resource's BufferSize to one
2021-12-01 22:31:28 -08:00
SIShrinkInstructions.cpp
[AMDGPU] SIShrinkInstructions: sink code to where it's used. NFC.
2021-12-13 14:46:40 +00:00
SIWholeQuadMode.cpp
[AMDGPU][SIWholeQuadMode] Use the right VCC register to activate the correct lanes.
2022-01-26 08:54:39 -08:00
SMInstructions.td
[AMDGPU] Mark time intrinsics as nomem, hassideeffects
2021-12-07 16:24:06 +00:00
SOPInstructions.td
[AMDGPU] Enable divergence-driven XNOR selection
2022-01-26 15:33:10 +03:00
VIInstrFormats.td
…
VOP1Instructions.td
[AMDGPU] Add an implicit use of M0 to all V_MOV_B32_indirect_read/write
2021-11-19 19:00:17 +00:00
VOP2Instructions.td
[AMDGPU] Enable divergence-driven XNOR selection
2022-01-26 15:33:10 +03:00
VOP3Instructions.td
[AMDGPU] Add constrained shift pattern matches.
2021-10-26 19:07:19 +05:30
VOP3PInstructions.td
[AMDGPU] Prevent aliasing of SrcC and Dst in MAI
2022-01-26 14:48:20 -08:00
VOPCInstructions.td
…
VOPInstructions.td
[AMDGPU] Changing S_AND_B32 to V_AND_B32_e64 in the divergent 'trunc' to i1 pattern
2021-12-24 18:24:49 +03:00