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llvm-project/llvm/test/CodeGen
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Stanislav Mekhanoshin d71924fbfe [AMDGPU] Improve v2i32/v2f32 insertelt patterns 
Using REG_SEQUENCE produces better code than INSERT_SUBREG,
we can omit one move instruction in many cases.

Fixes: SWDEV-298028

Differential Revision: https://reviews.llvm.org/D107602
2021-08-05 16:13:39 -07:00
..
AArch64
[AArch64][GlobalISel] Widen G_BSWAP before clamping
2021-08-05 15:16:00 -07:00
AMDGPU
[AMDGPU] Improve v2i32/v2f32 insertelt patterns
2021-08-05 16:13:39 -07:00
ARC
…
ARM
[ARM][atomicrmw] Fix CMP_SWAP_32 expand assert
2021-08-04 15:02:02 +01:00
AVR
[AVR] emit 'MCSA_Global' references to '__do_global_ctors' and '__do_global_dtors'
2021-08-05 10:37:36 +08:00
BPF
BPF: avoid NE/EQ loop exit condition
2021-08-04 16:54:16 -07:00
Generic
[PowerPC] Add pwr7 and pwr10 support to IBM MASSV pass on AIX
2021-07-26 23:21:38 +00:00
Hexagon
[Hexagon] Fix resetting dead registers in DBG_VALUE_LISTs
2021-07-27 18:36:28 -05:00
Inputs
…
Lanai
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
M68k
[M68k][GloballSel] LegalizerInfo implementation
2021-07-15 13:00:43 -06:00
Mips
GlobalISel/AArch64: don't optimize away redundant branches at -O0
2021-07-29 16:04:22 -07:00
MIR
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
MSP430
…
NVPTX
Fix the default alignment of i1 vectors.
2021-07-31 14:09:59 -07:00
PowerPC
[PowerPC] Remove accidently left checks
2021-08-05 22:46:07 +00:00
RISCV
[DAGCombiner][RISCV][AMDGPU] Call SimplifyDemandedBits at the end of visitMULHU to enable known bits contant folding.
2021-08-05 08:31:26 -07:00
SPARC
CodeGen: Print/parse LLTs in MachineMemOperands
2021-06-30 16:54:13 -04:00
SystemZ
[NFC][Codegen][SystemZ] Autogenerate checklines in int-cmp-47.ll
2021-08-04 01:47:39 +03:00
Thumb
[ARM] Regenerate Thumb PR35481.ll test. NFC
2021-07-31 16:21:23 +01:00
Thumb2
[Thumb2] generate checks in ldr-str-imm12.ll. NFC.
2021-08-05 14:58:02 -07:00
VE
[LegalizeTypes][VE] Don't Expand BITREVERSE/BSWAP during type legalization promotion if they will be promoted for NVT in op legalization.
2021-06-29 11:00:11 -07:00
WebAssembly
[WebAssembly] Don't do SjLj transformation when there's only setjmp
2021-08-05 15:28:02 -07:00
WinCFGuard
…
WinEH
…
X86
[NFC][Codegen][X86] Add testcase that hanged after D107009
2021-08-05 20:37:50 +03:00
XCore
Update @llvm.powi to handle different int sizes for the exponent
2021-06-17 09:38:28 +02:00