123064dc39
This cc1 option -fallow-half-arguments-and-returns allows __fp16 to be passed by argument and returned, without giving an error. It is currently always enabled for Arm and AArch64, by forcing the option in the driver. This means any cc1 tests (especially those needing arm_neon.h) need to specify the option too, to prevent the error from being emitted. This changes it to a target option instead, set to true for Arm and AArch64. This allows the option to be removed. Previously it was implied by -fnative_half_arguments_and_returns, which is set for certain languages like open_cl, renderscript and hlsl, so that option now too controls the errors. There were are few other non-arm uses of -fallow-half-arguments-and-returns but I believe they were unnecessary. The strictfp_builtins.c tests were converted from __fp16 to _Float16 to avoid the issues. Differential Revision: https://reviews.llvm.org/D133885
225 lines
12 KiB
C++
225 lines
12 KiB
C++
// NOTE: Assertions have been autogenerated by utils/update_cc_test_checks.py
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// RUN: %clang_cc1 -triple aarch64-none-linux-gnu -target-feature +sve \
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// RUN: -disable-O0-optnone \
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// RUN: -emit-llvm -o - %s | opt -S -sroa | FileCheck %s
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// REQUIRES: aarch64-registered-target
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#include <arm_sve.h>
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// CHECK-LABEL: @_Z9cond_boolu10__SVBool_tu10__SVBool_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 16 x i1> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 16 x i1> [[CMP]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 16 x i1> [[VECTOR_COND]], <vscale x 16 x i1> [[A]], <vscale x 16 x i1> [[B]]
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// CHECK-NEXT: ret <vscale x 16 x i1> [[VECTOR_SELECT]]
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//
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svbool_t cond_bool(svbool_t a, svbool_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z7cond_i8u10__SVInt8_tu10__SVInt8_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 16 x i8> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 16 x i1> [[VECTOR_COND]], <vscale x 16 x i8> [[A]], <vscale x 16 x i8> [[B]]
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// CHECK-NEXT: ret <vscale x 16 x i8> [[VECTOR_SELECT]]
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//
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svint8_t cond_i8(svint8_t a, svint8_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z7cond_u8u11__SVUint8_tu11__SVUint8_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 16 x i8> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 16 x i1> [[CMP]] to <vscale x 16 x i8>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 16 x i8> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 16 x i1> [[VECTOR_COND]], <vscale x 16 x i8> [[A]], <vscale x 16 x i8> [[B]]
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// CHECK-NEXT: ret <vscale x 16 x i8> [[VECTOR_SELECT]]
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//
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svuint8_t cond_u8(svuint8_t a, svuint8_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_i16u11__SVInt16_tu11__SVInt16_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 8 x i16> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 8 x i1> [[VECTOR_COND]], <vscale x 8 x i16> [[A]], <vscale x 8 x i16> [[B]]
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// CHECK-NEXT: ret <vscale x 8 x i16> [[VECTOR_SELECT]]
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//
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svint16_t cond_i16(svint16_t a, svint16_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_u16u12__SVUint16_tu12__SVUint16_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 8 x i16> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 8 x i16> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 8 x i1> [[VECTOR_COND]], <vscale x 8 x i16> [[A]], <vscale x 8 x i16> [[B]]
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// CHECK-NEXT: ret <vscale x 8 x i16> [[VECTOR_SELECT]]
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//
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svuint16_t cond_u16(svuint16_t a, svuint16_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_i32u11__SVInt32_tu11__SVInt32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]
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//
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svint32_t cond_i32(svint32_t a, svint32_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_u32u12__SVUint32_tu12__SVUint32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> [[B]]
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// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]
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//
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svuint32_t cond_u32(svuint32_t a, svuint32_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_i64u11__SVInt64_tu11__SVInt64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> [[B]]
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// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]
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//
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svint64_t cond_i64(svint64_t a, svint64_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_u64u12__SVUint64_tu12__SVUint64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> [[B]]
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// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]
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//
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svuint64_t cond_u64(svuint64_t a, svuint64_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_f16u13__SVFloat16_tu13__SVFloat16_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 8 x half> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 8 x i1> [[CMP]] to <vscale x 8 x i16>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 8 x i16> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 8 x i1> [[VECTOR_COND]], <vscale x 8 x half> [[A]], <vscale x 8 x half> [[B]]
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// CHECK-NEXT: ret <vscale x 8 x half> [[VECTOR_SELECT]]
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//
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svfloat16_t cond_f16(svfloat16_t a, svfloat16_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_f32u13__SVFloat32_tu13__SVFloat32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 4 x float> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x float> [[A]], <vscale x 4 x float> [[B]]
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// CHECK-NEXT: ret <vscale x 4 x float> [[VECTOR_SELECT]]
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//
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svfloat32_t cond_f32(svfloat32_t a, svfloat32_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z8cond_f64u13__SVFloat64_tu13__SVFloat64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 2 x double> [[A:%.*]], [[B:%.*]]
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x double> [[A]], <vscale x 2 x double> [[B]]
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// CHECK-NEXT: ret <vscale x 2 x double> [[VECTOR_SELECT]]
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//
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svfloat64_t cond_f64(svfloat64_t a, svfloat64_t b) {
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return a < b ? a : b;
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}
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// CHECK-LABEL: @_Z14cond_i32_splatu11__SVInt32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], zeroinitializer
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> zeroinitializer
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// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]
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//
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svint32_t cond_i32_splat(svint32_t a) {
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return a < 0 ? a : 0;
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}
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// CHECK-LABEL: @_Z14cond_u32_splatu12__SVUint32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 4 x i32> [[A:%.*]], shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x i32> [[A]], <vscale x 4 x i32> shufflevector (<vscale x 4 x i32> insertelement (<vscale x 4 x i32> poison, i32 1, i32 0), <vscale x 4 x i32> poison, <vscale x 4 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 4 x i32> [[VECTOR_SELECT]]
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//
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svuint32_t cond_u32_splat(svuint32_t a) {
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return a < 1u ? a : 1u;
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}
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// CHECK-LABEL: @_Z14cond_i64_splatu11__SVInt64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], zeroinitializer
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> zeroinitializer
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// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]
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//
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svint64_t cond_i64_splat(svint64_t a) {
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return a < 0l ? a : 0l;
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}
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// CHECK-LABEL: @_Z14cond_u64_splatu12__SVUint64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = icmp ult <vscale x 2 x i64> [[A:%.*]], shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x i64> [[A]], <vscale x 2 x i64> shufflevector (<vscale x 2 x i64> insertelement (<vscale x 2 x i64> poison, i64 1, i32 0), <vscale x 2 x i64> poison, <vscale x 2 x i32> zeroinitializer)
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// CHECK-NEXT: ret <vscale x 2 x i64> [[VECTOR_SELECT]]
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//
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svuint64_t cond_u64_splat(svuint64_t a) {
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return a < 1ul ? a : 1ul;
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}
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// CHECK-LABEL: @_Z14cond_f32_splatu13__SVFloat32_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 4 x float> [[A:%.*]], zeroinitializer
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 4 x i1> [[CMP]] to <vscale x 4 x i32>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 4 x i32> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 4 x i1> [[VECTOR_COND]], <vscale x 4 x float> [[A]], <vscale x 4 x float> zeroinitializer
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// CHECK-NEXT: ret <vscale x 4 x float> [[VECTOR_SELECT]]
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//
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svfloat32_t cond_f32_splat(svfloat32_t a) {
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return a < 0.f ? a : 0.f;
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}
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// CHECK-LABEL: @_Z14cond_f64_splatu13__SVFloat64_t(
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// CHECK-NEXT: entry:
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// CHECK-NEXT: [[CMP:%.*]] = fcmp olt <vscale x 2 x double> [[A:%.*]], zeroinitializer
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// CHECK-NEXT: [[CONV:%.*]] = zext <vscale x 2 x i1> [[CMP]] to <vscale x 2 x i64>
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// CHECK-NEXT: [[VECTOR_COND:%.*]] = icmp ne <vscale x 2 x i64> [[CONV]], zeroinitializer
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// CHECK-NEXT: [[VECTOR_SELECT:%.*]] = select <vscale x 2 x i1> [[VECTOR_COND]], <vscale x 2 x double> [[A]], <vscale x 2 x double> zeroinitializer
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// CHECK-NEXT: ret <vscale x 2 x double> [[VECTOR_SELECT]]
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//
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svfloat64_t cond_f64_splat(svfloat64_t a) {
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return a < 0. ? a : 0.;
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}
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