shylie/llvm-project
1
0
Fork 0
Code Issues Pull Requests Actions 6 Packages Projects Releases Wiki Activity
llvm-project/llvm/lib/Target/AMDGPU
History
Pierre van Houtryve 63390dccd8 [GlobalISel] Add Predicates to GICombineRule 
Small QoL change to allow Predicates to be used in GICombineRule.
Currently only one combine in the AMDGPU backend makes use of it.

The implementation is pretty simple to get started but of course we can expand this later on and optimize predicate checking better if needed.

Reviewed By: dsanders

Differential Revision: https://reviews.llvm.org/D136681
2022-10-26 07:13:40 +00:00
..
AsmParser
[AMDGPU] Fix delay alu for VOPD with src2acc
2022-10-25 13:11:17 -04:00
Disassembler
[AMDGPU] Make the uses_dynamic_stack field in the kernel descriptor and the metadata map specific to code object v5 and later
2022-10-11 23:28:43 +05:30
MCA
[MCA] Introducing incremental SourceMgr and resumable pipeline
2022-06-24 15:39:51 -07:00
MCTargetDesc
[AMDGPU][MC][GFX8+] Correct v_cndmask modifiers
2022-10-14 19:37:27 +03:00
TargetInfo
Fix shlib builds for all lib/Target/*/TargetInfo libs
2021-10-08 15:21:13 -07:00
Utils
[AMDGPU] Fix delay alu for VOPD with src2acc
2022-10-25 13:11:17 -04:00
AMDGPU.h
AMDGPU: Add a pass to rewrite certain undef in PHI
2022-09-26 09:54:47 +08:00
AMDGPU.td
[GlobalISel] Add Predicates to GICombineRule
2022-10-26 07:13:40 +00:00
AMDGPUAliasAnalysis.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
AMDGPUAliasAnalysis.h
[AA] Remove unused template argument from AAResultBase (NFC)
2022-10-06 10:21:17 +02:00
AMDGPUAlwaysInlinePass.cpp
[HIP] [AlwaysInliner] Disable AlwaysInliner to eliminate undefined symbols
2021-10-18 16:53:15 -06:00
AMDGPUAnnotateKernelFeatures.cpp
[AMDGPU][NFC] Correct typos in lib/Target/AMDGPU/AMDGPU*.cpp files. Test commit for new contributor.
2021-09-20 14:48:50 -07:00
AMDGPUAnnotateUniformValues.cpp
[AMDGPU] Return better Changed status from AMDGPUAnnotateUniformValues
2022-02-17 09:31:42 +00:00
AMDGPUArgumentUsageInfo.cpp
[amdgpu] Implement lds kernel id intrinsic
2022-07-19 17:46:19 +01:00
AMDGPUArgumentUsageInfo.h
[amdgpu] Implement lds kernel id intrinsic
2022-07-19 17:46:19 +01:00
AMDGPUAsmPrinter.cpp
[AMDGPU] Make the uses_dynamic_stack field in the kernel descriptor and the metadata map specific to code object v5 and later
2022-10-11 23:28:43 +05:30
AMDGPUAsmPrinter.h
[AMDGPU] Add remarks to output some resource usage
2022-07-15 11:01:53 -07:00
AMDGPUAtomicOptimizer.cpp
[AMDGPU] Add GFX11 llvm.amdgcn.permlane64 intrinsic
2022-06-13 21:12:11 +01:00
AMDGPUAttributes.def
[amdgpu] Implement lds kernel id intrinsic
2022-07-19 17:46:19 +01:00
AMDGPUAttributor.cpp
[Attributor] Teach AAPointerInfo to look into aggregates
2022-10-05 06:19:47 -07:00
AMDGPUCallingConv.td
[AMDGPU][NFC] Refactor AMDGPUCallingConv.td
2022-06-01 16:24:09 +00:00
AMDGPUCallLowering.cpp
[amdgpu][nfc] Allocate kernel-specific LDS struct deterministically
2022-09-28 14:55:16 +01:00
AMDGPUCallLowering.h
…
AMDGPUCodeGenPrepare.cpp
AMDGPU: Fix assertion on <1 x i16> vectors
2022-10-12 17:25:24 -07:00
AMDGPUCombine.td
[GlobalISel] Add Predicates to GICombineRule
2022-10-26 07:13:40 +00:00
AMDGPUCombinerHelper.cpp
[AMDGPU][GlobalISel] Fix insert point in FoldableFneg combine
2022-02-11 12:09:40 +01:00
AMDGPUCombinerHelper.h
[AMDGPU][GlobalISel] Fold G_FNEG above when users cannot fold mods
2021-11-17 14:25:13 +01:00
AMDGPUCtorDtorLowering.cpp
AMDGPU: Don't crash on global_ctor/dtor declaration
2022-06-23 21:04:54 +08:00
AMDGPUExportClustering.cpp
[llvm] Use = default (NFC)
2022-02-06 22:18:35 -08:00
AMDGPUExportClustering.h
…
AMDGPUFeatures.td
AMDGPU: Remove FeatureLocalMemorySize0
2021-09-02 22:43:01 -04:00
AMDGPUFrameLowering.cpp
[NFC][AMDGPU] Fix typo.
2022-08-20 08:30:42 +02:00
AMDGPUFrameLowering.h
…
AMDGPUGenRegisterBankInfo.def
…
AMDGPUGISel.td
[AMDGPU][CodeGen] Support (soffset + offset) s_buffer_load's.
2022-09-05 12:53:05 +01:00
AMDGPUGlobalISelUtils.cpp
[AMDGPU] Assume getDefIgnoringCopies will succeed. NFC.
2022-10-19 11:10:00 +01:00
AMDGPUGlobalISelUtils.h
[AMDGPU][CodeGen] Support (base | offset) SMEM loads.
2022-09-05 14:22:06 +01:00
AMDGPUHSAMetadataStreamer.cpp
[AMDGPU] Make the uses_dynamic_stack field in the kernel descriptor and the metadata map specific to code object v5 and later
2022-10-11 23:28:43 +05:30
AMDGPUHSAMetadataStreamer.h
[AMDGPU/Metadata] Rename HSAMD::MetadataStreamer classes
2022-09-06 16:46:37 -04:00
AMDGPUIGroupLP.cpp
[llvm] Use range-based for loops (NFC)
2022-09-03 23:27:25 -07:00
AMDGPUIGroupLP.h
[AMDGPU] Add iglp_opt builtin and MFMA GEMM Opt strategy
2022-08-19 15:38:36 -07:00
AMDGPUInsertDelayAlu.cpp
[AMDGPU] New AMDGPUInsertDelayAlu pass
2022-06-29 21:30:20 +01:00
AMDGPUInstCombineIntrinsic.cpp
[AMDGPU] Add new GFX11 intrinsic llvm.amdgcn.exp.row
2022-06-16 18:23:14 +01:00
AMDGPUInstrInfo.cpp
…
AMDGPUInstrInfo.h
[AMDGPU] Fix LOD bias in A16 combine
2022-01-21 12:09:06 +01:00
AMDGPUInstrInfo.td
[AMDGPU] Move call clobbered return address registers s[30:31] to callee saved range
2022-03-09 12:18:02 +05:30
AMDGPUInstructions.td
[AMDGPU] Use V_PERM to match buildvectors when inputs are not canonicalized (i.e. can't use V_PACK)
2022-10-03 12:58:29 -07:00
AMDGPUInstructionSelector.cpp
[AMDGPU][GISel] Constrain selected operands in selectG_BUILD_VECTOR
2022-10-21 06:50:16 +00:00
AMDGPUInstructionSelector.h
[AMDGPU] Always lower SHUFFLE_VECTOR
2022-10-04 14:23:17 +00:00
AMDGPUISelDAGToDAG.cpp
[AMDGPU] Add GFX11 ds_bvh_stack_rtn_b32 instruction
2022-09-15 16:46:14 +01:00
AMDGPUISelDAGToDAG.h
[AMDGPU] Add GFX11 ds_bvh_stack_rtn_b32 instruction
2022-09-15 16:46:14 +01:00
AMDGPUISelLowering.cpp
[AMDGPU][DAG] Fix trunc/shift combine condition
2022-10-21 06:36:07 +00:00
AMDGPUISelLowering.h
[X86] Promote i8/i16 CTTZ (BSF) instructions and remove speculation branch
2022-08-24 17:28:18 +01:00
AMDGPULateCodeGenPrepare.cpp
[AArch64, AMDGPU] Use make_early_inc_range (NFC)
2021-11-03 09:22:51 -07:00
AMDGPULegalizerInfo.cpp
[AMDGPU][GISel] Add missing V2S16 BUILD_VECTOR_TRUNC legalization
2022-10-06 06:48:53 +00:00
AMDGPULegalizerInfo.h
[AMDGPU] Always lower SHUFFLE_VECTOR
2022-10-04 14:23:17 +00:00
AMDGPULibCalls.cpp
try to fix build yet more after 16544cbe64b8
2022-09-28 15:40:52 -04:00
AMDGPULibFunc.cpp
[llvm] Use std::size instead of llvm::array_lengthof
2022-09-08 09:01:53 -06:00
AMDGPULibFunc.h
[llvm] Use = default (NFC)
2022-02-06 22:18:35 -08:00
AMDGPULowerIntrinsics.cpp
[iwyu] Handle regressions in libLLVM header include
2022-05-04 08:32:38 +02:00
AMDGPULowerKernelArguments.cpp
[NFC] Simplify code
2022-06-20 15:15:52 +00:00
AMDGPULowerKernelAttributes.cpp
[NFC][AMDGPULowerKernelAttributes] Factorize repeated code into function
2022-10-05 09:26:39 -05:00
AMDGPULowerModuleLDSPass.cpp
[amdgpu] Error, instead of miscompile, anonymous kernels using lds
2022-09-28 16:30:04 +01:00
AMDGPUMachineCFGStructurizer.cpp
[Target] Qualify auto in range-based for loops (NFC)
2022-08-28 10:41:50 -07:00
AMDGPUMachineFunction.cpp
[AMDGPU] Move SIModeRegisterDefaults to SI MFI
2022-09-28 13:13:40 -07:00
AMDGPUMachineFunction.h
[AMDGPU] Move SIModeRegisterDefaults to SI MFI
2022-09-28 13:13:40 -07:00
AMDGPUMachineModuleInfo.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
AMDGPUMachineModuleInfo.h
[llvm] Use value instead of getValue (NFC)
2022-07-13 23:11:56 -07:00
AMDGPUMacroFusion.cpp
…
AMDGPUMacroFusion.h
…
AMDGPUMCInstLower.cpp
[AMDGPU] Add iglp_opt builtin and MFMA GEMM Opt strategy
2022-08-19 15:38:36 -07:00
AMDGPUMCInstLower.h
AMDGPU: Fix missing c++ mode comment
2022-06-01 21:14:48 -04:00
AMDGPUMIRFormatter.cpp
CodeGen: Move getAddressSpaceForPseudoSourceKind into TargetMachine
2022-06-01 09:45:40 -04:00
AMDGPUMIRFormatter.h
[llvm] Remove redundaunt virtual specifiers (NFC)
2022-07-24 21:50:35 -07:00
AMDGPUOpenCLEnqueuedBlockLowering.cpp
[Target] Qualify auto in range-based for loops (NFC)
2022-08-28 10:41:50 -07:00
AMDGPUPerfHintAnalysis.cpp
[AMDGPU] Set amdgpu-memory-bound if a basic block has dense global memory access
2022-07-19 15:16:28 +05:30
AMDGPUPerfHintAnalysis.h
[AMDGPU] Set amdgpu-memory-bound if a basic block has dense global memory access
2022-07-19 15:16:28 +05:30
AMDGPUPostLegalizerCombiner.cpp
[GlobalISel] Add Predicates to GICombineRule
2022-10-26 07:13:40 +00:00
AMDGPUPreLegalizerCombiner.cpp
[GlobalISel] Allow prelegalizer combiners to have access to LegalizerInfo.
2022-10-03 07:36:18 +01:00
AMDGPUPrintfRuntimeBinding.cpp
[Target] Qualify auto in range-based for loops (NFC)
2022-08-28 10:41:50 -07:00
AMDGPUPromoteAlloca.cpp
Use llvm::less_second (NFC)
2022-06-04 22:48:32 -07:00
AMDGPUPromoteKernelArguments.cpp
[AMDGPU] Set noclobber metadata on loads instead of cast to constant
2022-03-07 23:13:02 -08:00
AMDGPUPropagateAttributes.cpp
AMDGPU: Use attributor to propagate amdgpu-flat-work-group-size
2021-10-22 16:23:50 -04:00
AMDGPUPTNote.h
[NFC] Fix endif comments to match with include guard
2022-01-07 15:52:59 +08:00
AMDGPURegBankCombiner.cpp
[GlobalISel] Allow prelegalizer combiners to have access to LegalizerInfo.
2022-10-03 07:36:18 +01:00
AMDGPURegisterBankInfo.cpp
[AMDGPU][GISel] Legalize V2S16 G_BUILD_VECTOR
2022-09-30 14:04:53 +00:00
AMDGPURegisterBankInfo.h
AMDGPU: Add G_AMDGPU_MAD_64_32 instructions
2022-05-27 12:36:17 -05:00
AMDGPURegisterBanks.td
…
AMDGPUReleaseVGPRs.cpp
[AMDGPU][Backend] Fix user-after-free in AMDGPUReleaseVGPRs::isLastVGPRUseVMEMStore
2022-10-19 04:38:16 -05:00
AMDGPUReplaceLDSUseWithPointer.cpp
[amdgpu][nfc] Factor predicate out of findLDSVariablesToLower
2022-08-31 15:44:51 +01:00
AMDGPUResourceUsageAnalysis.cpp
[AMDGPU] Report minimum scratch size in code object v5 and later by default
2022-09-29 09:52:45 +05:30
AMDGPUResourceUsageAnalysis.h
AMDGPU: Convert AMDGPUResourceUsageAnalysis to a Module pass
2022-02-04 15:56:04 -05:00
AMDGPURewriteOutArguments.cpp
Revert "[llvm] Use llvm::is_contained (NFC)"
2022-08-28 18:52:49 -07:00
AMDGPURewriteUndefForPHI.cpp
Add override for runOnFunction()
2022-09-26 10:19:35 +08:00
AMDGPUSearchableTables.td
[AMDGPU] Support for gfx940 fp8 smfmac
2022-07-18 12:12:41 -07:00
AMDGPUSetWavePriority.cpp
[AMDGPU][SetWavePriority] Fix dealing with MBBInfo records.
2022-09-30 14:27:50 +01:00
AMDGPUSubtarget.cpp
[AMDGPU] Add MIMG NSA threshold configuration attribute
2022-09-28 20:03:18 +09:00
AMDGPUSubtarget.h
[AMDGPU] gfx11 subtarget features & early tests
2022-05-11 10:31:49 -04:00
AMDGPUTargetMachine.cpp
AMDGPU: Add a pass to rewrite certain undef in PHI
2022-09-26 09:54:47 +08:00
AMDGPUTargetMachine.h
CodeGen: Move getAddressSpaceForPseudoSourceKind into TargetMachine
2022-06-01 09:45:40 -04:00
AMDGPUTargetObjectFile.cpp
…
AMDGPUTargetObjectFile.h
…
AMDGPUTargetTransformInfo.cpp
[AMDGPU] Limit TID / wavefrontsize uniformness to 1D kernels
2022-08-30 12:22:08 -07:00
AMDGPUTargetTransformInfo.h
[TTI] Use OperandValueInfo in getArithmeticInstrCost implementation [NFC]
2022-08-22 15:16:39 -07:00
AMDGPUUnifyDivergentExitNodes.cpp
[AMDGPU] Unify unreachable intrinsics
2022-08-09 10:23:32 -04:00
AMDGPUUnifyMetadata.cpp
[Target] Qualify auto in range-based for loops (NFC)
2022-08-28 10:41:50 -07:00
AMDKernelCodeT.h
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
BUFInstructions.td
AMDGPU: Use tablegen patterns for buffer global and flat atomic fadd
2022-09-23 17:52:10 +02:00
CaymanInstructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
CMakeLists.txt
AMDGPU: Add a pass to rewrite certain undef in PHI
2022-09-26 09:54:47 +08:00
DSInstructions.td
[AMDGPU] Pattern for flat atomic fadd f64 intrinsic with local addr
2022-09-25 13:25:41 +02:00
EvergreenInstructions.td
Code quality: Combine V_RSQ
2021-11-30 17:17:15 +01:00
EXPInstructions.td
[AMDGPU] Add new GFX11 intrinsic llvm.amdgcn.exp.row
2022-06-16 18:23:14 +01:00
FLATInstructions.td
AMDGPU: Use tablegen patterns for buffer global and flat atomic fadd
2022-09-23 17:52:10 +02:00
GCNCreateVOPD.cpp
[AMDGPU][GFX11][NFC] Refactor VOPD handling in codegen
2022-10-07 16:13:05 +03:00
GCNDPPCombine.cpp
[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C
2022-09-20 09:56:28 -04:00
GCNHazardRecognizer.cpp
AMDGPU: Fix hazard with v_accvgpr_write_b32 and inline asm VGPR defs
2022-10-12 17:25:24 -07:00
GCNHazardRecognizer.h
[AMDGPU][GFX11] Mitigate VALU mask write hazard
2022-10-01 16:21:24 +09:00
GCNILPSched.cpp
[llvm] Qualify auto in range-based for loops (NFC)
2022-08-13 12:55:42 -07:00
GCNIterativeScheduler.cpp
[Target] Qualify auto in range-based for loops (NFC)
2022-08-28 10:41:50 -07:00
GCNIterativeScheduler.h
…
GCNMinRegStrategy.cpp
[llvm] Qualify auto in range-based for loops (NFC)
2022-08-13 12:55:42 -07:00
GCNNSAReassign.cpp
[AMDGPU] GFX11 CodeGen support for MIMG instructions
2022-06-16 18:23:14 +01:00
GCNPreRAOptimizations.cpp
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
GCNProcessors.td
[AMDGPU] user-sgpr-init16-bug does not apply to gfx1103
2022-07-29 14:21:13 +01:00
GCNRegPressure.cpp
[NFC] Use Register instead of unsigned
2022-01-19 20:17:04 +08:00
GCNRegPressure.h
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
GCNSchedStrategy.cpp
[AMDGPU] Add iglp_opt builtin and MFMA GEMM Opt strategy
2022-08-19 15:38:36 -07:00
GCNSchedStrategy.h
[AMDGPU] Add iglp_opt builtin and MFMA GEMM Opt strategy
2022-08-19 15:38:36 -07:00
GCNSubtarget.h
[AMDGPU][GFX11] Mitigate VALU mask write hazard
2022-10-01 16:21:24 +09:00
GCNVOPDUtils.cpp
[AMDGPU][GFX11][NFC] Refactor VOPD handling in codegen
2022-10-07 16:13:05 +03:00
GCNVOPDUtils.h
[AMDGPU] gfx11 Generate VOPD Instructions
2022-07-05 09:18:19 -04:00
InstCombineTables.td
…
LDSDIRInstructions.td
[AMDGPU] gfx11 ldsdir intrinsics and ISel
2022-06-17 09:03:16 -04:00
MIMGInstructions.td
[AMDGPU][MC] Correct image_gather4h
2022-10-11 14:41:27 +03:00
R600.h
[AMDGPU] Rename AMDGPUCFGStructurizer to R600MachineCFGStructurizer
2022-02-18 15:08:25 +00:00
R600.td
[AMDGPU] Fix useDeprecatedPositionallyEncodedOperands errors in R600.
2022-09-25 17:55:09 -04:00
R600AsmPrinter.cpp
[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC
2022-08-08 11:24:15 -07:00
R600AsmPrinter.h
…
R600ClauseMergePass.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
R600ControlFlowFinalizer.cpp
[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC
2022-08-08 11:24:15 -07:00
R600Defines.h
…
R600EmitClauseMarkers.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
R600ExpandSpecialInstrs.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
R600FrameLowering.cpp
Cleanup codegen includes
2022-03-16 08:43:00 +01:00
R600FrameLowering.h
…
R600InstrFormats.td
…
R600InstrInfo.cpp
CodeGen: Move getAddressSpaceForPseudoSourceKind into TargetMachine
2022-06-01 09:45:40 -04:00
R600InstrInfo.h
CodeGen: Move getAddressSpaceForPseudoSourceKind into TargetMachine
2022-06-01 09:45:40 -04:00
R600InstrInfo.td
…
R600Instructions.td
[AMDGPU] Fix useDeprecatedPositionallyEncodedOperands errors in R600.
2022-09-25 17:55:09 -04:00
R600ISelDAGToDAG.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
R600ISelLowering.cpp
[llvm] LLVM_FALLTHROUGH => [[fallthrough]]. NFC
2022-08-08 11:24:15 -07:00
R600ISelLowering.h
[llvm] Remove redundaunt virtual specifiers (NFC)
2022-07-24 21:50:35 -07:00
R600MachineCFGStructurizer.cpp
[AMDGPU] Fix -Wunused-variable in -DLLVM_ENABLE_ASSERTIONS=off builds
2022-04-19 22:36:58 -07:00
R600MachineFunctionInfo.cpp
…
R600MachineFunctionInfo.h
…
R600MachineScheduler.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
R600MachineScheduler.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
R600MCInstLower.cpp
[CodeGen] Move instruction predicate verification to emitInstruction
2022-07-14 09:33:28 +01:00
R600OpenCLImageTypeLoweringPass.cpp
[llvm] Use range-based for loops (NFC)
2021-12-11 11:29:12 -08:00
R600OptimizeVectorRegisters.cpp
[Target] Use range-based for loops (NFC)
2021-12-17 10:11:08 -08:00
R600Packetizer.cpp
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
R600Processors.td
AMDGPU: Remove FeatureLocalMemorySize0
2021-09-02 22:43:01 -04:00
R600RegisterInfo.cpp
[llvm] Use std::size instead of llvm::array_lengthof
2022-09-08 09:01:53 -06:00
R600RegisterInfo.h
…
R600RegisterInfo.td
…
R600Schedule.td
…
R600Subtarget.cpp
[AMDGPU] Use default member initializers in Subtarget classes
2022-04-12 16:42:30 +01:00
R600Subtarget.h
[AMDGPU] Use default member initializers in Subtarget classes
2022-04-12 16:42:30 +01:00
R600TargetMachine.cpp
mark getTargetTransformInfo and getTargetIRAnalysis as const
2022-02-25 14:30:44 -05:00
R600TargetMachine.h
mark getTargetTransformInfo and getTargetIRAnalysis as const
2022-02-25 14:30:44 -05:00
R600TargetTransformInfo.cpp
[NFC][AMDGPU] Reduce includes dependencies, part 2
2021-10-01 17:50:20 +03:00
R600TargetTransformInfo.h
[AArch64][TTI][NFC] Overload method 'getVectorInstrCost' to provide vector instruction itself, as a context information for cost estimation.
2022-08-04 12:58:25 -07:00
R700Instructions.td
…
SIAnnotateControlFlow.cpp
[AMDGPU] Return better Changed status from SIAnnotateControlFlow
2022-02-17 09:38:57 +00:00
SIDefines.h
[AMDGPU] gfx11 WMMA instruction support
2022-06-30 11:13:45 -04:00
SIFixSGPRCopies.cpp
[AMDGPU] SIFixSGPRCopies reworking to use one pass over the MIR for analysis and lowering.
2022-09-19 23:31:45 +02:00
SIFixVGPRCopies.cpp
…
SIFoldOperands.cpp
[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C
2022-09-20 09:56:28 -04:00
SIFormMemoryClauses.cpp
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
SIFrameLowering.cpp
[AMDGPU] Fix prologue/epilogue markers in .debug_line table for trivial functions
2022-08-10 23:00:19 +05:30
SIFrameLowering.h
[AMDGPU] On gfx908, reserve VGPR for AGPR copy based on register budget.
2022-04-21 07:57:26 +05:30
SIInsertHardClauses.cpp
[AMDGPU] Update SIInsertHardClauses for GFX11
2022-06-09 21:29:56 +01:00
SIInsertWaitcnts.cpp
[AMDGPU] New helper function SIInsertWaitcnts::getVmemWaitEventType
2022-10-19 16:22:50 +01:00
SIInstrFormats.td
[AMDGPU][MC][GFX11] Correct disassembly of *_e64_dpp opcodes which support op_sel
2022-07-15 13:11:59 +03:00
SIInstrInfo.cpp
[AMDGPU] Use Register in more places in SIInstrInfo. NFC.
2022-10-25 15:04:58 +01:00
SIInstrInfo.h
[AMDGPU] Use Register in more places in SIInstrInfo. NFC.
2022-10-25 15:04:58 +01:00
SIInstrInfo.td
[AMDGPU][MC] Correct v_cndmask operand types
2022-10-20 15:09:35 +03:00
SIInstructions.td
[AMDGPU] Use VGPR classes in divergent build_vector patterns
2022-10-21 16:57:23 +01:00
SIISelLowering.cpp
[AMDGPU][DAG] Fix insert_vector_elt lowering for 8 bit elements
2022-10-04 14:48:15 +00:00
SIISelLowering.h
[AMDGPU] Always select s_cselect_b32 for uniform 'select' SDNode
2022-09-15 22:03:56 +02:00
SILateBranchLowering.cpp
[Target] Qualify auto in range-based for loops (NFC)
2022-08-28 10:41:50 -07:00
SILoadStoreOptimizer.cpp
[AMDGPU][SILoadStoreOptimizer] Merge SGPR_IMM scalar buffer loads.
2022-09-15 13:48:51 +01:00
SILowerControlFlow.cpp
[AMDGPU] SILowerControlFlow uses LiveIntervals
2022-07-12 16:53:53 +01:00
SILowerI1Copies.cpp
AMDGPU: Factor out hasDivergentBranch(). NFC
2022-09-14 13:27:21 +08:00
SILowerSGPRSpills.cpp
AMDGPU: Update SlotIndexes independently of LiveIntervals
2022-10-07 13:15:15 -07:00
SIMachineFunctionInfo.cpp
[AMDGPU] Move SIModeRegisterDefaults to SI MFI
2022-09-28 13:13:40 -07:00
SIMachineFunctionInfo.h
[AMDGPU] Move SIModeRegisterDefaults to SI MFI
2022-09-28 13:13:40 -07:00
SIMachineScheduler.cpp
[AMDGPU] SIMachineScheduler: Add support for several MachineScheduler features
2022-07-14 09:45:31 +02:00
SIMachineScheduler.h
[AMDGPU][NFC] Fix typos
2021-11-12 11:37:21 +01:00
SIMemoryLegalizer.cpp
[AMDGPU][NFC] Fix typo in commment: replace SiMemOpInfo by SIMemOpInfo
2022-09-02 16:45:10 +02:00
SIModeRegister.cpp
[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C
2022-09-20 09:56:28 -04:00
SIOptimizeExecMasking.cpp
[NFC][AMDGPU] Some cleanups in the SIOptimizeExecMasking pass.
2022-08-23 18:16:47 +02:00
SIOptimizeExecMaskingPreRA.cpp
[AMDGPU] Improve liveness copying in si-optimize-exec-masking-pre-ra
2022-07-17 17:34:05 +09:00
SIOptimizeVGPRLiveRange.cpp
AMDGPU: Skip unexpected CFG in SIOptimizeVGPRLiveRange
2022-06-22 12:49:41 +08:00
SIPeepholeSDWA.cpp
[AMDGPU][NFC] Fix typos
2022-02-18 15:05:21 +01:00
SIPostRABundler.cpp
[AMDGPU] Use llvm::any_of (NFC)
2022-10-16 09:19:09 -07:00
SIPreAllocateWWMRegs.cpp
AMDGPU: Defer creation of WWM VGPR spill slots
2022-04-19 21:07:13 -04:00
SIPreEmitPeephole.cpp
[Target] Qualify auto in range-based for loops (NFC)
2022-08-28 10:41:50 -07:00
SIProgramInfo.cpp
…
SIProgramInfo.h
[AMDGPU] Add remarks to output some resource usage
2022-07-15 11:01:53 -07:00
SIRegisterInfo.cpp
AMDGPU: Update SlotIndexes independently of LiveIntervals
2022-10-07 13:15:15 -07:00
SIRegisterInfo.h
AMDGPU: Update SlotIndexes independently of LiveIntervals
2022-10-07 13:15:15 -07:00
SIRegisterInfo.td
[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C
2022-09-20 09:56:28 -04:00
SISchedule.td
[AMDGPU] gfx11 subtarget features & early tests
2022-05-11 10:31:49 -04:00
SIShrinkInstructions.cpp
[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C
2022-09-20 09:56:28 -04:00
SIWholeQuadMode.cpp
TableGen: Introduce generated getSubRegisterClass function
2022-09-12 09:03:37 -04:00
SMInstructions.td
[AMDGPU][CodeGen] Support (soffset + offset) s_buffer_load's.
2022-09-05 12:53:05 +01:00
SOPInstructions.td
[AMDGPU] Use V_PERM to match buildvectors when inputs are not canonicalized (i.e. can't use V_PACK)
2022-10-03 12:58:29 -07:00
VIInstrFormats.td
[AMDGPU] gfx11 export instructions
2022-05-25 14:44:09 -04:00
VINTERPInstructions.td
[AMDGPU] gfx11 VINTERP intrinsics and ISel support
2022-06-17 09:16:59 -04:00
VOP1Instructions.td
[AMDGPU] Make V_SAT_PK_U8_I16 a True16 Instruction
2022-10-10 10:33:49 -04:00
VOP2Instructions.td
[AMDGPU] Fix delay alu for VOPD with src2acc
2022-10-25 13:11:17 -04:00
VOP3Instructions.td
[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C
2022-09-20 09:56:28 -04:00
VOP3PInstructions.td
[AMDGPU][MC][GFX940] Correct disassembly of MFMA opcodes
2022-08-01 16:00:47 +03:00
VOPCInstructions.td
[AMDGPU][MC] Correct definition of aliases
2022-10-24 17:06:52 +03:00
VOPDInstructions.td
[AMDGPU] Fix delay alu for VOPD with src2acc
2022-10-25 13:11:17 -04:00
VOPInstructions.td
[AMDGPU][GFX11] Use VGPR_32_Lo128 for VOP1,2,C
2022-09-20 09:56:28 -04:00