1e4f82c257
This patch adds the assembly/disassembly for the following instructions: ADD (to vector): Add replicated single vector to multi-vector with multi-vector result. SQDMULH (multiple and single vector): Multi-vector signed saturating doubling multiply high by vector. for 2 and 4 ZA SVE registers. The reference can be found here: https://developer.arm.com/documentation/ddi0602/2022-09 It also adds more size for the multiple register tuple: ZZ_b_mul_r, ZZ_h_mul_r, ZZZZ_b_mul_r, ZZZZ_h_mul_r, for 8 bits and 16 bits with 2 and 4 ZA registers. Depends on: D135468 With a fix for Mips for this test: llvm/test/MC/Mips/mips64r6/valid.s Differential Revision: https://reviews.llvm.org/D135563