fbdea5a2e9
This patch contains changes necessary to carry physical condition register (SCC) dependencies through the SDNode scheduler. It adds the edge in the SDNodeScheduler dependency graph instead of inserting the SCC copy between each definition and use. This approach lets the scheduler place instructions in an optimal way placing the copy only when the dependency cannot be resolved. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D133593
105 lines
3.7 KiB
LLVM
105 lines
3.7 KiB
LLVM
; RUN: llc -march=amdgcn -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=SI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=bonaire -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s
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; RUN: llc -march=amdgcn -mcpu=tonga -verify-machineinstrs < %s | FileCheck -allow-deprecated-dag-overlap -check-prefix=CI -check-prefix=FUNC %s
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declare double @llvm.ceil.f64(double) nounwind readnone
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declare <2 x double> @llvm.ceil.v2f64(<2 x double>) nounwind readnone
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declare <3 x double> @llvm.ceil.v3f64(<3 x double>) nounwind readnone
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declare <4 x double> @llvm.ceil.v4f64(<4 x double>) nounwind readnone
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declare <8 x double> @llvm.ceil.v8f64(<8 x double>) nounwind readnone
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declare <16 x double> @llvm.ceil.v16f64(<16 x double>) nounwind readnone
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; FUNC-LABEL: {{^}}fceil_f64:
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; CI: v_ceil_f64_e32
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; SI: s_bfe_u32 [[SEXP:s[0-9]+]], {{s[0-9]+}}, 0xb0014
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; SI-DAG: s_and_b32 s{{[0-9]+}}, s{{[0-9]+}}, 0x80000000
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; SI-DAG: s_addk_i32 [[SEXP]], 0xfc01
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; SI-DAG: s_lshr_b64 s[{{[0-9]+:[0-9]+}}], s[{{[0-9]+:[0-9]+}}], [[SEXP]]
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; SI-DAG: s_andn2_b64
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; SI-DAG: cmp_gt_i32
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; SI-DAG: s_cselect_b32
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; SI-DAG: s_cselect_b32
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; SI-DAG: cmp_lt_i32
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; SI-DAG: s_cselect_b32
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; SI-DAG: s_cselect_b32
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; SI-DAG: v_cmp_gt_f64_e64 [[FCMP:s[[0-9]+:[0-9]+]]]
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; SI-DAG: v_cmp_lg_f64_e32 vcc
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; SI-DAG: s_and_b64 [[AND1:s[[0-9]+:[0-9]+]]], [[FCMP]], vcc
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; SI-DAG: s_and_b64 [[AND1]], [[AND1]], exec
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; SI-DAG: s_cselect_b32 s{{[0-9]+}}, 0x3ff00000, 0
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; SI: v_add_f64
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; SI: s_endpgm
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define amdgpu_kernel void @fceil_f64(double addrspace(1)* %out, double %x) {
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%y = call double @llvm.ceil.f64(double %x) nounwind readnone
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store double %y, double addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v2f64:
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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define amdgpu_kernel void @fceil_v2f64(<2 x double> addrspace(1)* %out, <2 x double> %x) {
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%y = call <2 x double> @llvm.ceil.v2f64(<2 x double> %x) nounwind readnone
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store <2 x double> %y, <2 x double> addrspace(1)* %out
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ret void
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}
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; FIXME-FUNC-LABEL: {{^}}fceil_v3f64:
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; FIXME-CI: v_ceil_f64_e32
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; FIXME-CI: v_ceil_f64_e32
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; FIXME-CI: v_ceil_f64_e32
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; define amdgpu_kernel void @fceil_v3f64(<3 x double> addrspace(1)* %out, <3 x double> %x) {
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; %y = call <3 x double> @llvm.ceil.v3f64(<3 x double> %x) nounwind readnone
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; store <3 x double> %y, <3 x double> addrspace(1)* %out
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; ret void
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; }
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; FUNC-LABEL: {{^}}fceil_v4f64:
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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define amdgpu_kernel void @fceil_v4f64(<4 x double> addrspace(1)* %out, <4 x double> %x) {
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%y = call <4 x double> @llvm.ceil.v4f64(<4 x double> %x) nounwind readnone
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store <4 x double> %y, <4 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v8f64:
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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define amdgpu_kernel void @fceil_v8f64(<8 x double> addrspace(1)* %out, <8 x double> %x) {
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%y = call <8 x double> @llvm.ceil.v8f64(<8 x double> %x) nounwind readnone
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store <8 x double> %y, <8 x double> addrspace(1)* %out
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ret void
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}
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; FUNC-LABEL: {{^}}fceil_v16f64:
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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; CI: v_ceil_f64_e32
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define amdgpu_kernel void @fceil_v16f64(<16 x double> addrspace(1)* %out, <16 x double> %x) {
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%y = call <16 x double> @llvm.ceil.v16f64(<16 x double> %x) nounwind readnone
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store <16 x double> %y, <16 x double> addrspace(1)* %out
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ret void
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}
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