db0a658c61
Change a couple of RUN lines to not depend on the presence or position of the IR code sinking pass in the codegen pipeline, since it does not belong in there anyway.
29 lines
1.4 KiB
LLVM
29 lines
1.4 KiB
LLVM
; RUN: llc -march=amdgcn -mcpu=tahiti -start-before=amdgpu-unify-divergent-exit-nodes -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; RUN: llc -enable-no-signed-zeros-fp-math -march=amdgcn -mcpu=tahiti -start-before=amdgpu-unify-divergent-exit-nodes -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefix=GCN %s
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; --------------------------------------------------------------------------------
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; rcp_legacy tests
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; --------------------------------------------------------------------------------
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; GCN-LABEL: {{^}}v_fneg_rcp_legacy_f32:
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; GCN: {{buffer|flat}}_load_dword [[A:v[0-9]+]]
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; GCN: v_rcp_legacy_f32_e64 [[RESULT:v[0-9]+]], -[[A]]
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; GCN: {{buffer|flat}}_store_dword [[RESULT]]
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define amdgpu_kernel void @v_fneg_rcp_legacy_f32(float addrspace(1)* %out, float addrspace(1)* %a.ptr) #0 {
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%tid = call i32 @llvm.amdgcn.workitem.id.x()
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%tid.ext = sext i32 %tid to i64
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%a.gep = getelementptr inbounds float, float addrspace(1)* %a.ptr, i64 %tid.ext
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%out.gep = getelementptr inbounds float, float addrspace(1)* %out, i64 %tid.ext
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%a = load volatile float, float addrspace(1)* %a.gep
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%rcp = call float @llvm.amdgcn.rcp.legacy(float %a)
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%fneg = fsub float -0.000000e+00, %rcp
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store float %fneg, float addrspace(1)* %out.gep
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ret void
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}
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declare i32 @llvm.amdgcn.workitem.id.x() #1
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declare float @llvm.amdgcn.rcp.legacy(float) #1
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attributes #0 = { nounwind }
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attributes #1 = { nounwind readnone }
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