7a84624079
Surprisingly these were getting legalized to something zero initialized. This fixes an infinite loop when combining some vector types. Also fixes zero initializing some undef values. SimplifyDemandedVectorElts / SimplifyDemandedBits are not checking for the legality of the output undefs they are replacing unused operations with. This resulted in turning vectors into undefs that were later re-legalized back into zero vectors.
263 lines
7.5 KiB
LLVM
263 lines
7.5 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=gfx900 < %s | FileCheck -check-prefix=GCN %s
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; GCN-LABEL: {{^}}select_undef_lhs:
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; GCN: s_waitcnt
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; GCN-NOT: v_cmp
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; GCN-NOT: v_cndmask
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; GCN-NEXT: s_setpc_b64
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define float @select_undef_lhs(float %val, i1 %cond) {
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%undef = call float @llvm.amdgcn.rcp.f32(float undef)
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%sel = select i1 %cond, float %undef, float %val
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ret float %sel
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}
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; GCN-LABEL: {{^}}select_undef_rhs:
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; GCN: s_waitcnt
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; GCN-NOT: v_cmp
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; GCN-NOT: v_cndmask
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; GCN-NEXT: s_setpc_b64
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define float @select_undef_rhs(float %val, i1 %cond) {
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%undef = call float @llvm.amdgcn.rcp.f32(float undef)
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%sel = select i1 %cond, float %val, float %undef
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ret float %sel
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}
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; GCN-LABEL: {{^}}select_undef_n1:
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; GCN: v_mov_b32_e32 [[RES:v[0-9]+]], 1.0
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; GCN: store_dword {{[^,]+}}, [[RES]]
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define void @select_undef_n1(float addrspace(1)* %a, i32 %c) {
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%cc = icmp eq i32 %c, 0
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%sel = select i1 %cc, float 1.000000e+00, float undef
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store float %sel, float addrspace(1)* %a
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ret void
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}
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; GCN-LABEL: {{^}}select_undef_n2:
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; GCN: v_mov_b32_e32 [[RES:v[0-9]+]], 1.0
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; GCN: store_dword {{[^,]+}}, [[RES]]
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define void @select_undef_n2(float addrspace(1)* %a, i32 %c) {
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%cc = icmp eq i32 %c, 0
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%sel = select i1 %cc, float undef, float 1.000000e+00
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store float %sel, float addrspace(1)* %a
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ret void
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}
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declare float @llvm.amdgcn.rcp.f32(float)
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; Make sure the vector undef isn't lowered into 0s.
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; GCN-LABEL: {{^}}undef_v6f32:
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN-NOT: s_mov_b32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_vccnz
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define amdgpu_kernel void @undef_v6f32(<6 x float> addrspace(3)* %ptr, i1 %cond) {
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entry:
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br label %loop
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loop:
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%phi = phi <6 x float> [ undef, %entry ], [ %add, %loop ]
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%load = load volatile <6 x float>, <6 x float> addrspace(3)* undef
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%add = fadd <6 x float> %load, %phi
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br i1 %cond, label %loop, label %ret
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ret:
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store volatile <6 x float> %add, <6 x float> addrspace(3)* undef
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ret void
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}
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; GCN-LABEL: {{^}}undef_v6i32:
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN-NOT: s_mov_b32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_vccnz
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define amdgpu_kernel void @undef_v6i32(<6 x i32> addrspace(3)* %ptr, i1 %cond) {
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entry:
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br label %loop
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loop:
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%phi = phi <6 x i32> [ undef, %entry ], [ %add, %loop ]
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%load = load volatile <6 x i32>, <6 x i32> addrspace(3)* undef
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%add = add <6 x i32> %load, %phi
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br i1 %cond, label %loop, label %ret
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ret:
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store volatile <6 x i32> %add, <6 x i32> addrspace(3)* undef
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ret void
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}
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; Make sure the vector undef isn't lowered into 0s.
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; GCN-LABEL: {{^}}undef_v5f32:
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN-NOT: s_mov_b32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_vccnz
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define amdgpu_kernel void @undef_v5f32(<5 x float> addrspace(3)* %ptr, i1 %cond) {
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entry:
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br label %loop
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loop:
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%phi = phi <5 x float> [ undef, %entry ], [ %add, %loop ]
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%load = load volatile <5 x float>, <5 x float> addrspace(3)* undef
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%add = fadd <5 x float> %load, %phi
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br i1 %cond, label %loop, label %ret
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ret:
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store volatile <5 x float> %add, <5 x float> addrspace(3)* undef
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ret void
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}
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; GCN-LABEL: {{^}}undef_v5i32:
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN-NOT: s_mov_b32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_vccnz
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define amdgpu_kernel void @undef_v5i32(<5 x i32> addrspace(3)* %ptr, i1 %cond) {
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entry:
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br label %loop
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loop:
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%phi = phi <5 x i32> [ undef, %entry ], [ %add, %loop ]
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%load = load volatile <5 x i32>, <5 x i32> addrspace(3)* undef
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%add = add <5 x i32> %load, %phi
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br i1 %cond, label %loop, label %ret
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ret:
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store volatile <5 x i32> %add, <5 x i32> addrspace(3)* undef
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ret void
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}
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; Make sure the vector undef isn't lowered into 0s.
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; GCN-LABEL: {{^}}undef_v3f64:
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN-NOT: s_mov_b32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_vccnz
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define amdgpu_kernel void @undef_v3f64(<3 x double> addrspace(3)* %ptr, i1 %cond) {
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entry:
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br label %loop
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loop:
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%phi = phi <3 x double> [ undef, %entry ], [ %add, %loop ]
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%load = load volatile <3 x double>, <3 x double> addrspace(3)* %ptr
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%add = fadd <3 x double> %load, %phi
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br i1 %cond, label %loop, label %ret
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ret:
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store volatile <3 x double> %add, <3 x double> addrspace(3)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}undef_v3i64:
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN-NOT: s_mov_b32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_vccnz
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define amdgpu_kernel void @undef_v3i64(<3 x i64> addrspace(3)* %ptr, i1 %cond) {
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entry:
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br label %loop
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loop:
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%phi = phi <3 x i64> [ undef, %entry ], [ %add, %loop ]
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%load = load volatile <3 x i64>, <3 x i64> addrspace(3)* %ptr
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%add = add <3 x i64> %load, %phi
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br i1 %cond, label %loop, label %ret
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ret:
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store volatile <3 x i64> %add, <3 x i64> addrspace(3)* %ptr
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ret void
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}
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; Make sure the vector undef isn't lowered into 0s.
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; GCN-LABEL: {{^}}undef_v4f16:
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN-NOT: s_mov_b32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_vccnz
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define amdgpu_kernel void @undef_v4f16(<4 x half> addrspace(3)* %ptr, i1 %cond) {
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entry:
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br label %loop
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loop:
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%phi = phi <4 x half> [ undef, %entry ], [ %add, %loop ]
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%load = load volatile <4 x half>, <4 x half> addrspace(3)* %ptr
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%add = fadd <4 x half> %load, %phi
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br i1 %cond, label %loop, label %ret
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ret:
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store volatile <4 x half> %add, <4 x half> addrspace(3)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}undef_v4i16:
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN-NOT: s_mov_b32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_vccnz
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define amdgpu_kernel void @undef_v4i16(<4 x i16> addrspace(3)* %ptr, i1 %cond) {
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entry:
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br label %loop
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loop:
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%phi = phi <4 x i16> [ undef, %entry ], [ %add, %loop ]
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%load = load volatile <4 x i16>, <4 x i16> addrspace(3)* %ptr
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%add = add <4 x i16> %load, %phi
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br i1 %cond, label %loop, label %ret
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ret:
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store volatile <4 x i16> %add, <4 x i16> addrspace(3)* %ptr
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ret void
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}
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; Make sure the vector undef isn't lowered into 0s.
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; GCN-LABEL: {{^}}undef_v2f16:
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN-NOT: s_mov_b32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_vccnz
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define amdgpu_kernel void @undef_v2f16(<2 x half> addrspace(3)* %ptr, i1 %cond) {
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entry:
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br label %loop
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loop:
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%phi = phi <2 x half> [ undef, %entry ], [ %add, %loop ]
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%load = load volatile <2 x half>, <2 x half> addrspace(3)* %ptr
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%add = fadd <2 x half> %load, %phi
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br i1 %cond, label %loop, label %ret
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ret:
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store volatile <2 x half> %add, <2 x half> addrspace(3)* %ptr
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ret void
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}
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; GCN-LABEL: {{^}}undef_v2i16:
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; GCN-NOT: v_mov_b32_e32 v{{[0-9]+}}, 0
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; GCN-NOT: s_mov_b32 s{{[0-9]+}}, 0
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; GCN: s_cbranch_vccnz
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define amdgpu_kernel void @undef_v2i16(<2 x i16> addrspace(3)* %ptr, i1 %cond) {
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entry:
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br label %loop
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loop:
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%phi = phi <2 x i16> [ undef, %entry ], [ %add, %loop ]
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%load = load volatile <2 x i16>, <2 x i16> addrspace(3)* %ptr
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%add = add <2 x i16> %load, %phi
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br i1 %cond, label %loop, label %ret
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ret:
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store volatile <2 x i16> %add, <2 x i16> addrspace(3)* %ptr
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ret void
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}
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; We were expanding undef vectors into zero vectors. Optimizations
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; would then see we used no elements of the vector, and reform the
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; undef vector resulting in a combiner loop.
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; GCN-LABEL: {{^}}inf_loop_undef_vector:
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; GCN: s_waitcnt
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; GCN-NEXT: v_mad_u64_u32
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; GCN-NEXT: v_mul_lo_u32
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; GCN-NEXT: v_mul_lo_u32
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; GCN-NEXT: v_add3_u32
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; GCN-NEXT: global_store_dwordx2
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define void @inf_loop_undef_vector(<6 x float> %arg, float %arg1, i64 %arg2) {
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%i = insertelement <6 x float> %arg, float %arg1, i64 2
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%i3 = bitcast <6 x float> %i to <3 x i64>
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%i4 = extractelement <3 x i64> %i3, i64 0
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%i5 = extractelement <3 x i64> %i3, i64 1
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%i6 = mul i64 %i5, %arg2
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%i7 = add i64 %i6, %i4
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store volatile i64 %i7, i64 addrspace(1)* undef, align 4
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ret void
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}
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