fbdea5a2e9
This patch contains changes necessary to carry physical condition register (SCC) dependencies through the SDNode scheduler. It adds the edge in the SDNodeScheduler dependency graph instead of inserting the SCC copy between each definition and use. This approach lets the scheduler place instructions in an optimal way placing the copy only when the dependency cannot be resolved. Reviewed By: rampitec Differential Revision: https://reviews.llvm.org/D133593
127 lines
4.8 KiB
LLVM
127 lines
4.8 KiB
LLVM
; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=hawaii -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,SI %s
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; RUN: llc -mtriple=amdgcn-amd-amdhsa -mcpu=fiji -verify-machineinstrs < %s | FileCheck -enable-var-scope -check-prefixes=GCN,VI %s
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declare i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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; GCN-LABEL: {{^}}v_uint_to_fp_i64_to_f64
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; GCN: flat_load_dwordx2 v[[[LO:[0-9]+]]:[[HI:[0-9]+]]]
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; GCN-DAG: v_cvt_f64_u32_e32 [[HI_CONV:v\[[0-9]+:[0-9]+\]]], v[[HI]]
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; GCN-DAG: v_cvt_f64_u32_e32 [[LO_CONV:v\[[0-9]+:[0-9]+\]]], v[[LO]]
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; GCN-DAG: v_ldexp_f64 [[LDEXP:v\[[0-9]+:[0-9]+\]]], [[HI_CONV]], 32
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; GCN: v_add_f64 [[RESULT:v\[[0-9]+:[0-9]+\]]], [[LDEXP]], [[LO_CONV]]
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; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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define amdgpu_kernel void @v_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 addrspace(1)* %in) {
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%tid = call i32 @llvm.amdgcn.workitem.id.x() nounwind readnone
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%gep = getelementptr i64, i64 addrspace(1)* %in, i32 %tid
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%val = load i64, i64 addrspace(1)* %gep, align 8
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%result = uitofp i64 %val to double
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store double %result, double addrspace(1)* %out
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ret void
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}
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; GCN-LABEL: {{^}}s_uint_to_fp_i64_to_f64
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define amdgpu_kernel void @s_uint_to_fp_i64_to_f64(double addrspace(1)* %out, i64 %in) {
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%cast = uitofp i64 %in to double
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store double %cast, double addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}s_uint_to_fp_v2i64_to_v2f64
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define amdgpu_kernel void @s_uint_to_fp_v2i64_to_v2f64(<2 x double> addrspace(1)* %out, <2 x i64> %in) {
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%cast = uitofp <2 x i64> %in to <2 x double>
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store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}s_uint_to_fp_v4i64_to_v4f64
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define amdgpu_kernel void @s_uint_to_fp_v4i64_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i64> %in) {
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%cast = uitofp <4 x i64> %in to <4 x double>
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store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}s_uint_to_fp_i32_to_f64
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; GCN: v_cvt_f64_u32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @s_uint_to_fp_i32_to_f64(double addrspace(1)* %out, i32 %in) {
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%cast = uitofp i32 %in to double
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store double %cast, double addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}s_uint_to_fp_v2i32_to_v2f64
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; GCN: v_cvt_f64_u32_e32
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; GCN: v_cvt_f64_u32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @s_uint_to_fp_v2i32_to_v2f64(<2 x double> addrspace(1)* %out, <2 x i32> %in) {
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%cast = uitofp <2 x i32> %in to <2 x double>
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store <2 x double> %cast, <2 x double> addrspace(1)* %out, align 16
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ret void
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}
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; GCN-LABEL: {{^}}s_uint_to_fp_v4i32_to_v4f64
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; GCN: v_cvt_f64_u32_e32
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; GCN: v_cvt_f64_u32_e32
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; GCN: v_cvt_f64_u32_e32
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; GCN: v_cvt_f64_u32_e32
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; GCN: s_endpgm
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define amdgpu_kernel void @s_uint_to_fp_v4i32_to_v4f64(<4 x double> addrspace(1)* %out, <4 x i32> %in) {
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%cast = uitofp <4 x i32> %in to <4 x double>
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store <4 x double> %cast, <4 x double> addrspace(1)* %out, align 16
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ret void
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}
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; We can't fold the SGPRs into v_cndmask_b32_e32, because it already
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; uses an SGPR (implicit vcc).
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; GCN-LABEL: {{^}}uint_to_fp_i1_to_f64:
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; VI-DAG: s_cmp_eq_u32
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; GCN-DAG: s_cselect_b32 s[[SSEL:[0-9]+]], 0x3ff00000, 0
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; GCN-DAG: v_mov_b32_e32 v[[ZERO:[0-9]+]], 0{{$}}
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; GCN-DAG: v_mov_b32_e32 v[[SEL:[0-9]+]], s[[SSEL]]
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; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, v[[[ZERO]]:[[SEL]]]
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; GCN: s_endpgm
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define amdgpu_kernel void @uint_to_fp_i1_to_f64(double addrspace(1)* %out, i32 %in) {
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%cmp = icmp eq i32 %in, 0
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%fp = uitofp i1 %cmp to double
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store double %fp, double addrspace(1)* %out, align 4
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ret void
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}
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; GCN-LABEL: {{^}}uint_to_fp_i1_to_f64_load:
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; GCN: v_cndmask_b32_e64 [[IRESULT:v[0-9]]], 0, 1
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; GCN: v_cvt_f64_u32_e32 [[RESULT:v\[[0-9]+:[0-9]\]]], [[IRESULT]]
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; GCN: flat_store_dwordx2 v{{\[[0-9]+:[0-9]+\]}}, [[RESULT]]
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; GCN: s_endpgm
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define amdgpu_kernel void @uint_to_fp_i1_to_f64_load(double addrspace(1)* %out, i1 %in) {
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%fp = uitofp i1 %in to double
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store double %fp, double addrspace(1)* %out, align 8
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ret void
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}
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; GCN-LABEL: {{^}}s_uint_to_fp_i8_to_f64:
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; GCN: s_load_dword [[VAL:s[0-9]+]]
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; SI: s_and_b32 [[ZEXT:s[0-9]+]], [[VAL]], 0xff{{$}}
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; SI: v_cvt_f64_u32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[ZEXT]]
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; VI: s_and_b32 [[ZEXT:s[0-9]+]], [[VAL]], 0xff{{$}}
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; VI: v_cvt_f64_u32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[ZEXT]]
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define amdgpu_kernel void @s_uint_to_fp_i8_to_f64(double addrspace(1)* %out, i8 %in) {
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%fp = uitofp i8 %in to double
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store double %fp, double addrspace(1)* %out
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ret void
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}
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; FIXME: Worse on VI
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; GCN-LABEL: {{^}}v_uint_to_fp_i8_to_f64:
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; SI: v_and_b32_e32 [[ZEXT:v[0-9]+]], 0xff, v0
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; SI: v_cvt_f64_u32_e32 v{{\[[0-9]+:[0-9]+\]}}, [[ZEXT]]
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; VI: v_mov_b32_e32 v{{[0-9]+}}
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; VI: v_and_b32_sdwa
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; VI: v_cvt_f64_u32_e32 v{{\[[0-9]+:[0-9]+\]}},
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define double @v_uint_to_fp_i8_to_f64(i8 %in) {
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%fp = uitofp i8 %in to double
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ret double %fp
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}
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