3a20597776
Implement an intrinsic for use lowering LDS variables to different addresses from different kernels. This will allow kernels that cannot reach an LDS variable to avoid wasting space for it. There are a number of implicit arguments accessed by intrinsic already so this implementation closely follows the existing handling. It is slightly novel in that this SGPR is written by the kernel prologue. It is necessary in the general case to put variables at different addresses such that they can be compactly allocated and thus necessary for an indirect function call to have some means of determining where a given variable was allocated. Claiming an arbitrary SGPR into which an integer can be written by the kernel, in this implementation based on metadata associated with that kernel, which is then passed on to indirect call sites is sufficient to determine the variable address. The intent is to emit a __const array of LDS addresses and index into it. Reviewed By: arsenm Differential Revision: https://reviews.llvm.org/D125060
103 lines
3.3 KiB
LLVM
103 lines
3.3 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_test_checks.py UTC_ARGS: --function-signature --check-globals
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; RUN: opt -S -mtriple=amdgcn-unknown-unknown -amdgpu-attributor < %s | FileCheck %s
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;.
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; CHECK: @[[G1:[a-zA-Z0-9_$"\\.-]+]] = global i32* null
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; CHECK: @[[G2:[a-zA-Z0-9_$"\\.-]+]] = global i32 0
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;.
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define weak void @weak() {
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; CHECK-LABEL: define {{[^@]+}}@weak
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; CHECK-SAME: () #[[ATTR0:[0-9]+]] {
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; CHECK-NEXT: call void @internal1()
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; CHECK-NEXT: ret void
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;
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call void @internal1()
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ret void
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}
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@G1 = global i32* null
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define internal void @internal1() {
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; CHECK-LABEL: define {{[^@]+}}@internal1
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; CHECK-SAME: () #[[ATTR0]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i32*, i32** @G1, align 8
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; CHECK-NEXT: store i32 0, i32* [[TMP1]], align 4
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; CHECK-NEXT: ret void
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;
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%1 = load i32*, i32** @G1
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store i32 0, i32* %1
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ret void
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}
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define amdgpu_kernel void @kernel1() #0 {
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; CHECK-LABEL: define {{[^@]+}}@kernel1
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; CHECK-SAME: () #[[ATTR1:[0-9]+]] {
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; CHECK-NEXT: call void @weak()
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; CHECK-NEXT: ret void
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;
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call void @weak()
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ret void
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}
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@G2 = global i32 0
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define internal void @internal3() {
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; CHECK-LABEL: define {{[^@]+}}@internal3
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; CHECK-SAME: () #[[ATTR1]] {
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; CHECK-NEXT: [[TMP1:%.*]] = load i32, i32* @G2, align 4
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; CHECK-NEXT: [[TMP2:%.*]] = icmp eq i32 [[TMP1]], 0
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; CHECK-NEXT: br i1 [[TMP2]], label [[TMP3:%.*]], label [[TMP4:%.*]]
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; CHECK: 3:
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; CHECK-NEXT: call void @internal4()
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; CHECK-NEXT: call void @internal3()
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; CHECK-NEXT: br label [[TMP4]]
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; CHECK: 4:
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; CHECK-NEXT: ret void
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;
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%1 = load i32, i32* @G2, align 4
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%2 = icmp eq i32 %1, 0
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br i1 %2, label %3, label %4
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3:
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call void @internal4()
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call void @internal3()
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br label %4
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4:
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ret void
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}
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define internal void @internal4() {
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; CHECK-LABEL: define {{[^@]+}}@internal4
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; CHECK-SAME: () #[[ATTR1]] {
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; CHECK-NEXT: store i32 1, i32* @G2, align 4
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; CHECK-NEXT: ret void
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;
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store i32 1, i32* @G2, align 4
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ret void
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}
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define internal void @internal2() {
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; CHECK-LABEL: define {{[^@]+}}@internal2
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; CHECK-SAME: () #[[ATTR1]] {
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; CHECK-NEXT: call void @internal3()
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; CHECK-NEXT: ret void
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;
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call void @internal3()
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ret void
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}
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define amdgpu_kernel void @kernel2() #0 {
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; CHECK-LABEL: define {{[^@]+}}@kernel2
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; CHECK-SAME: () #[[ATTR1]] {
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; CHECK-NEXT: call void @internal2()
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; CHECK-NEXT: ret void
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;
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call void @internal2()
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ret void
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}
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attributes #0 = { "uniform-work-group-size"="true" }
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;.
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; CHECK: attributes #[[ATTR0]] = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="false" }
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; CHECK: attributes #[[ATTR1]] = { "amdgpu-no-dispatch-id" "amdgpu-no-dispatch-ptr" "amdgpu-no-heap-ptr" "amdgpu-no-hostcall-ptr" "amdgpu-no-implicitarg-ptr" "amdgpu-no-lds-kernel-id" "amdgpu-no-multigrid-sync-arg" "amdgpu-no-queue-ptr" "amdgpu-no-workgroup-id-x" "amdgpu-no-workgroup-id-y" "amdgpu-no-workgroup-id-z" "amdgpu-no-workitem-id-x" "amdgpu-no-workitem-id-y" "amdgpu-no-workitem-id-z" "uniform-work-group-size"="true" }
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;.
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