427fb35192
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, amyk, nikic, PowerPC Differential Revision: https://reviews.llvm.org/D135470
70 lines
2.4 KiB
LLVM
70 lines
2.4 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -O3 -mcpu=pwr9 -verify-machineinstrs -mtriple=powerpc64le-unknown-unknown < %s | FileCheck %s
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define dso_local void @wibble(ptr nocapture readonly %arg, i32 signext %arg1, ptr nocapture %arg2, ptr nocapture %arg3) {
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; CHECK-LABEL: wibble:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: lfs 0, 0(3)
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; CHECK-NEXT: li 7, 7
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; CHECK-NEXT: cmpwi 4, 2
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; CHECK-NEXT: xsaddsp 0, 0, 0
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; CHECK-NEXT: blt 0, .LBB0_5
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; CHECK-NEXT: # %bb.1: # %bb6
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; CHECK-NEXT: clrldi 4, 4, 32
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; CHECK-NEXT: li 7, 7
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; CHECK-NEXT: addi 4, 4, -1
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; CHECK-NEXT: mtctr 4
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; CHECK-NEXT: li 4, 8
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; CHECK-NEXT: b .LBB0_3
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB0_2: # %bb11
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; CHECK-NEXT: #
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; CHECK-NEXT: iselgt 7, 4, 7
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; CHECK-NEXT: addi 4, 4, 1
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; CHECK-NEXT: bdz .LBB0_5
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; CHECK-NEXT: .LBB0_3: # %bb11
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; CHECK-NEXT: #
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; CHECK-NEXT: lfsu 1, 4(3)
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; CHECK-NEXT: fcmpu 0, 1, 0
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; CHECK-NEXT: ble 0, .LBB0_2
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; CHECK-NEXT: # %bb.4:
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; CHECK-NEXT: xsaddsp 0, 1, 1
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; CHECK-NEXT: b .LBB0_2
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; CHECK-NEXT: .LBB0_5: # %bb8
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; CHECK-NEXT: stw 7, 0(5)
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; CHECK-NEXT: stfs 0, 0(6)
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; CHECK-NEXT: blr
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bb:
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%tmp = load float, ptr %arg, align 4
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%tmp4 = fmul float %tmp, 2.000000e+00
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%tmp5 = icmp sgt i32 %arg1, 1
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br i1 %tmp5, label %bb6, label %bb8
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bb6: ; preds = %bb
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%tmp7 = zext i32 %arg1 to i64
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br label %bb11
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bb8: ; preds = %bb11, %bb
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%tmp9 = phi float [ %tmp4, %bb ], [ %tmp19, %bb11 ]
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%tmp10 = phi i32 [ 7, %bb ], [ %tmp22, %bb11 ]
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store i32 %tmp10, ptr %arg2, align 4
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store float %tmp9, ptr %arg3, align 4
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ret void
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bb11: ; preds = %bb11, %bb6
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%tmp12 = phi i64 [ 1, %bb6 ], [ %tmp23, %bb11 ]
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%tmp13 = phi i32 [ 7, %bb6 ], [ %tmp22, %bb11 ]
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%tmp14 = phi float [ %tmp4, %bb6 ], [ %tmp19, %bb11 ]
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%tmp15 = getelementptr inbounds float, ptr %arg, i64 %tmp12
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%tmp16 = load float, ptr %tmp15, align 4
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%tmp17 = fcmp ogt float %tmp16, %tmp14
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%tmp18 = fmul float %tmp16, 2.000000e+00
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%tmp19 = select i1 %tmp17, float %tmp18, float %tmp14
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%tmp20 = trunc i64 %tmp12 to i32
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%tmp21 = add i32 %tmp20, 7
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%tmp22 = select i1 %tmp17, i32 %tmp21, i32 %tmp13
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%tmp23 = add nuw nsw i64 %tmp12, 1
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%tmp24 = icmp eq i64 %tmp23, %tmp7
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br i1 %tmp24, label %bb8, label %bb11
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}
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