5403c59c60
The LIT test cases were migrated with the script provided by Nikita Popov. Due to the size of the change it is split into several parts. Reviewed By: nemanja, nikic Differential Revision: https://reviews.llvm.org/D135474
75 lines
2.5 KiB
LLVM
75 lines
2.5 KiB
LLVM
; NOTE: Assertions have been autogenerated by utils/update_llc_test_checks.py
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; RUN: llc -ppc-asm-full-reg-names -verify-machineinstrs \
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; RUN: -mtriple=powerpc64le-unknown-linux-gnu -mcpu=pwr8 < %s | FileCheck %s
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; We don't want to produce a CTR loop due to the call to lrint in the body.
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define dso_local void @test(i64 %arg, i64 %arg1) {
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; CHECK-LABEL: test:
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; CHECK: # %bb.0: # %bb
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; CHECK-NEXT: bc 4, 4*cr5+lt, .LBB0_5
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; CHECK-NEXT: # %bb.1: # %bb3
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; CHECK-NEXT: bc 12, 4*cr5+lt, .LBB0_6
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; CHECK-NEXT: # %bb.2: # %bb4
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; CHECK-NEXT: mflr r0
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; CHECK-NEXT: .cfi_def_cfa_offset 64
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; CHECK-NEXT: .cfi_offset lr, 16
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; CHECK-NEXT: .cfi_offset r29, -24
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; CHECK-NEXT: .cfi_offset r30, -16
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; CHECK-NEXT: std r29, -24(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r30, -16(r1) # 8-byte Folded Spill
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; CHECK-NEXT: std r0, 16(r1)
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; CHECK-NEXT: stdu r1, -64(r1)
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; CHECK-NEXT: sub r30, r4, r3
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; CHECK-NEXT: li r29, -4
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; CHECK-NEXT: .p2align 5
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; CHECK-NEXT: .LBB0_3: # %bb5
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; CHECK-NEXT: #
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; CHECK-NEXT: lfsu f1, 4(r29)
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; CHECK-NEXT: bl lrint
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; CHECK-NEXT: nop
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; CHECK-NEXT: addi r30, r30, -1
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; CHECK-NEXT: cmpldi r30, 0
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; CHECK-NEXT: bne cr0, .LBB0_3
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; CHECK-NEXT: # %bb.4: # %bb15
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; CHECK-NEXT: stb r3, 0(r3)
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; CHECK-NEXT: addi r1, r1, 64
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; CHECK-NEXT: ld r0, 16(r1)
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; CHECK-NEXT: ld r30, -16(r1) # 8-byte Folded Reload
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; CHECK-NEXT: ld r29, -24(r1) # 8-byte Folded Reload
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; CHECK-NEXT: mtlr r0
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; CHECK-NEXT: blr
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; CHECK-NEXT: .LBB0_5: # %bb2
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; CHECK-NEXT: .LBB0_6: # %bb14
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bb:
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br i1 undef, label %bb3, label %bb2
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bb2: ; preds = %bb
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unreachable
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bb3: ; preds = %bb
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%tmp = sub i64 %arg1, %arg
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br i1 undef, label %bb4, label %bb14
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bb4: ; preds = %bb3
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br label %bb5
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bb5: ; preds = %bb5, %bb4
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%tmp6 = phi i64 [ %tmp12, %bb5 ], [ 0, %bb4 ]
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%tmp7 = getelementptr inbounds float, ptr null, i64 %tmp6
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%tmp8 = load float, ptr %tmp7, align 4
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%tmp9 = fpext float %tmp8 to double
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%tmp10 = tail call i64 @llvm.lrint.i64.f64(double %tmp9) #2
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%tmp11 = trunc i64 %tmp10 to i8
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store i8 %tmp11, ptr undef, align 1
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%tmp12 = add nuw i64 %tmp6, 1
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%tmp13 = icmp eq i64 %tmp12, %tmp
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br i1 %tmp13, label %bb15, label %bb5
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bb14: ; preds = %bb3
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unreachable
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bb15: ; preds = %bb5
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ret void
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}
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declare i64 @llvm.lrint.i64.f64(double)
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